diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 8a11d5c08..b95e27d1a 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -14,8 +14,9 @@ model = "Texas Instruments AM654 Base Board"; aliases { - ethernet1 = &icssg2_emac0; - ethernet2 = &icssg2_emac1; + ethernet1 = &icssg1_emac0; + //ethernet2 = &icssg1_emac1; //EtherCAT port 1 + ethernet2 = &icssg2_emac0; }; chosen { @@ -25,9 +26,9 @@ memory@80000000 { device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; + + /* 1G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; }; reserved-memory { @@ -66,64 +67,140 @@ }; rtos_ipc_memory_region: ipc-memories@a2000000 { - reg = <0x00 0xa2000000 0x00 0x00100000>; + reg = <0x00 0xa2000000 0x00 0x00200000>; alignment = <0x1000>; no-map; }; }; - gpio-keys { - compatible = "gpio-keys"; - autorepeat; + eeprom_gpio: eeprom_gpio { + compatible = "eeprom-gpio"; + eeprom-gpio = <&wkup_gpio0 7 GPIO_ACTIVE_HIGH>; + }; + + clk_ov5640_fixed: fixed-clock-ov5640 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + leds { pinctrl-names = "default"; - pinctrl-0 = <&push_button_pins_default>; + pinctrl-0 = <&ledgpio0_pins_default &ledgpio1_pins_default &ledgpio2_pins_default>; + + compatible = "gpio-leds"; - sw5 { - label = "GPIO Key USER1"; - linux,code = ; - gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>; + led1 { + label = "LED-RUN"; + gpios = <&main_gpio0 27 GPIO_ACTIVE_LOW>; }; - sw6 { - label = "GPIO Key USER2"; - linux,code = ; - gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; + led2 { + label = "LED-ERR"; + gpios = <&main_gpio1 70 GPIO_ACTIVE_HIGH>; }; - }; - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; + led3 { + label = "LED-BUS"; + gpios = <&main_gpio1 48 GPIO_ACTIVE_HIGH>; + }; - vcc3v3_io: fixedregulator-vcc3v3io { - /* Output of TPS54334 */ - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&evm_12v0>; - }; + led4 { + label = "LED-232TX"; + gpios = <&main_gpio1 21 GPIO_ACTIVE_HIGH>; + }; - vdd_mmc1_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vcc3v3_io>; - gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; + led5 { + label = "LED-232RX"; + gpios = <&main_gpio1 45 GPIO_ACTIVE_HIGH>; + }; + + led6 { + label = "LED-485TX"; + gpios = <&main_gpio1 87 GPIO_ACTIVE_HIGH>; + }; + + led7 { + label = "LED-485RX"; + gpios = <&main_gpio1 46 GPIO_ACTIVE_HIGH>; + }; + + led8 { + label = "LED-SD"; + gpios = <&main_gpio1 47 GPIO_ACTIVE_HIGH>; + }; }; - /* Dual Ethernet application node on PRU-ICSSG2 */ +#if 1 + /* Dual Ethernet application node on PRU-ICSSG1 */ + icssg1_eth: icssg1-eth { + compatible = "ti,am654-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_rgmii_pins_default>; + sram = <&msmc_ram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + mii-g-rt = <&icssg1_mii_g_rt>; + mii-rt = <&icssg1_mii_rt>; + iep = <&icssg1_iep0>, <&icssg1_iep1>; + + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + + interrupt-names = "tx_ts0", "tx_ts1"; + + dmas = <&main_udmap 0xc200>, /* egress slice 0 */ + <&main_udmap 0xc201>, /* egress slice 0 */ + <&main_udmap 0xc202>, /* egress slice 0 */ + <&main_udmap 0xc203>, /* egress slice 0 */ + <&main_udmap 0xc204>, /* egress slice 1 */ + <&main_udmap 0xc205>, /* egress slice 1 */ + <&main_udmap 0xc206>, /* egress slice 1 */ + <&main_udmap 0xc207>, /* egress slice 1 */ + + <&main_udmap 0x4200>, /* ingress slice 0 */ + <&main_udmap 0x4201>, /* ingress slice 1 */ + <&main_udmap 0x4202>, /* mgmnt rsp slice 0 */ + <&main_udmap 0x4203>; /* mgmnt rsp slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1", + "rxmgm0", "rxmgm1"; + + icssg1_emac0: ethernet-mii0 { + phy-handle = <&icssg1_phy0>; + phy-mode = "rgmii-rxid"; + syscon-rgmii-delay = <&scm_conf 0x4110>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + //ti,half-duplex-capable; + }; +#if 0 + icssg1_emac1: ethernet-mii1 { + phy-handle = <&icssg1_phy1>; + phy-mode = "rgmii-rxid"; + syscon-rgmii-delay = <&scm_conf 0x4114>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + //ti,half-duplex-capable; + }; +#endif + }; +#if 1 + /* Single Ethernet application node on PRU-ICSSG2 */ icssg2_eth: icssg2-eth { compatible = "ti,am654-icssg-prueth"; pinctrl-names = "default"; @@ -172,111 +249,176 @@ "rxmgm0", "rxmgm1"; icssg2_emac0: ethernet-mii0 { - phy-handle = <&icssg2_phy0>; + phy-handle = <&icssg2_phy2>; phy-mode = "rgmii-rxid"; syscon-rgmii-delay = <&scm_conf 0x4120>; /* Filled in by bootloader */ local-mac-address = [00 00 00 00 00 00]; }; - - icssg2_emac1: ethernet-mii1 { - phy-handle = <&icssg2_phy1>; - phy-mode = "rgmii-rxid"; - syscon-rgmii-delay = <&scm_conf 0x4124>; - /* Filled in by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - }; }; +#endif +#endif + }; &wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-names = "default"; + pinctrl-0 = <&eepromgpio_pins_default &iovolctrl_pins_default &i2c0switch_pins_default>; + + phy2ax58100_pins_default: phy2ax58100_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ - AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */ + AM65X_WKUP_IOPAD(0x0058, PIN_INPUT, 1) /* (N4) MCU_RGMII1_TX_CTL.MCU_RMII1_CRS_DV */ + AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 1) /* (N5) MCU_RGMII1_RX_CTL.MCU_RMII1_RX_ER */ + AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 1) /* (M4) MCU_RGMII1_TD1.MCU_RMII1_TXD1 */ + AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 1) /* (M5) MCU_RGMII1_TD0.MCU_RMII1_TXD0 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 1) /* (M6) MCU_RGMII1_RD1.MCU_RMII1_RXD1 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 1) /* (L6) MCU_RGMII1_RD0.MCU_RMII1_RXD0 */ + AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 1) /* (N1) MCU_RGMII1_TXC.MCU_RMII1_TX_EN */ + AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 1) /* (M1) MCU_RGMII1_RXC.MCU_RMII1_REF_CLK */ >; }; - push_button_pins_default: push-button-pins-default { + mcan0_pins_default: mcan0_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ - AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ + AM65X_WKUP_IOPAD(0x00ac, PIN_INPUT, 0) /* (W2) MCU_MCAN0_RX */ + AM65X_WKUP_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (W1) MCU_MCAN0_TX */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + phy2ax58100_mdio2_pins_default: phy2ax58100_mdio2_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */ - AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */ - AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */ - AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */ - AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */ - AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */ - AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */ - AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */ - AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */ - AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */ - AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */ + AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; - wkup_pca554_default: wkup-pca554-default { + eepromgpio_pins_default: eepromgpio_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ + AM65X_WKUP_IOPAD(0x00cc, PIN_INPUT, 7) /* (AC1) WKUP_GPIO0_7 */ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + iovolctrl_pins_default: iovolctrl_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ - AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ - AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */ - AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */ - AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */ - AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */ - AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */ - AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ - AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ - AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ - AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */ - AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ + AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AC2) WKUP_GPIO0_6 */ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + i2c0switch_pins_default: i2c0switch_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ - AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + AM65X_WKUP_IOPAD(0x00D8, PIN_OUTPUT, 7) /* (AB3) WKUP_GPIO0_10 */ >; }; }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_pins_default &gpio1_pins_default>; + + gpio1_pins_default: gpio1_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ - AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ - AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ - AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ + AM65X_IOPAD(0x01ec, PIN_OUTPUT, 7) /* (AG11) GPIO1_27 */ /*Latch*/ + AM65X_IOPAD(0x01f0, PIN_INPUT, 7) /* (AD11) GPIO1_28 */ /*/DO-FAULT*/ + AM65X_IOPAD(0x01f4, PIN_INPUT, 1) /* (V24) PRG0_PRU0_GPO0.GPIO1_29 */ + AM65X_IOPAD(0x01f8, PIN_INPUT, 1) /* (W25) PRG0_PRU0_GPO1.GPIO1_30 */ + AM65X_IOPAD(0x01fc, PIN_INPUT, 1) /* (W24) PRG0_PRU0_GPO2.GPIO1_31 */ + AM65X_IOPAD(0x0200, PIN_INPUT, 1) /* (AA27) PRG0_PRU0_GPO3.GPIO1_32 */ + AM65X_IOPAD(0x0204, PIN_INPUT, 1) /* (Y24) PRG0_PRU0_GPO4.GPIO1_33 */ + AM65X_IOPAD(0x0208, PIN_INPUT, 1) /* (V28) PRG0_PRU0_GPO5.GPIO1_34 */ + AM65X_IOPAD(0x020c, PIN_INPUT, 1) /* (Y25) PRG0_PRU0_GPO6.GPIO1_35 */ + AM65X_IOPAD(0x0210, PIN_INPUT, 1) /* (U27) PRG0_PRU0_GPO7.GPIO1_36 */ + AM65X_IOPAD(0x0214, PIN_INPUT, 7) /* (V27) PRG0_PRU0_GPO8.GPIO1_37 */ + AM65X_IOPAD(0x0218, PIN_INPUT, 7) /* (V26) PRG0_PRU0_GPO9.GPIO1_38 */ + AM65X_IOPAD(0x021c, PIN_INPUT, 7) /* (U25) PRG0_PRU0_GPO10.GPIO1_39 */ + AM65X_IOPAD(0x0220, PIN_INPUT, 7) /* (AB25) PRG0_PRU0_GPO11.GPIO1_40 */ + AM65X_IOPAD(0x0224, PIN_INPUT, 7) /* (AD27) PRG0_PRU0_GPO12.GPIO1_41 */ + AM65X_IOPAD(0x0228, PIN_INPUT, 7) /* (AC26) PRG0_PRU0_GPO13.GPIO1_42 */ + AM65X_IOPAD(0x022c, PIN_INPUT, 7) /* (AD26) PRG0_PRU0_GPO14.GPIO1_43 */ + AM65X_IOPAD(0x0230, PIN_INPUT, 7) /* (AA24) PRG0_PRU0_GPO15.GPIO1_44 */ + AM65X_IOPAD(0x0244, PIN_OUTPUT_PULLDOWN, 7) /* (AB28) PRG0_PRU1_GPO0.GPIO1_49 */ /*****************************************************************************/ + AM65X_IOPAD(0x0248, PIN_OUTPUT_PULLDOWN, 7) /* (AC28) PRG0_PRU1_GPO1.GPIO1_50 */ /*We set the mode as 7 due to PRU cannot control default status of output pin*/ + AM65X_IOPAD(0x024c, PIN_OUTPUT_PULLDOWN, 7) /* (AC27) PRG0_PRU1_GPO2.GPIO1_51 */ /*And we set the mode back to 0 using memdev2 after PRU init*/ + AM65X_IOPAD(0x0250, PIN_OUTPUT_PULLDOWN, 7) /* (AB26) PRG0_PRU1_GPO3.GPIO1_52 */ /*****************************************************************************/ + AM65X_IOPAD(0x0254, PIN_INPUT, 1) /* (AA25) PRG0_PRU1_GPI4.GPIO1_53 */ /*HS_PRU0_LV*/ + AM65X_IOPAD(0x0258, PIN_OUTPUT_PULLDOWN, 7) /* (U23) PRG0_PRU1_GPI4.GPIO1_54 */ /*HS_PRU0_IRQ*/ + AM65X_IOPAD(0x0284, PIN_INPUT, 7) /* (AC24) PRG0_PRU1_GPO16.GPIO1_65 */ + AM65X_IOPAD(0x028c, PIN_INPUT, 7) /* (Y26) PRG0_PRU1_GPO18.GPIO1_67 */ + AM65X_IOPAD(0x0290, PIN_INPUT, 7) /* (W26) PRG0_PRU1_GPO19.GPIO1_68 */ + AM65X_IOPAD(0x0294, PIN_INPUT, 7) /* (AE26) PRG0_MDIO0_MDIO.GPIO1_69 */ + AM65X_IOPAD(0x01d0, PIN_OUTPUT_PULLDOWN, 7) /* (AD12) GPIO1_20 */ /*SEL-OUT*/ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + ledgpio1_pins_default: ledgpio1_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */ - AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ + AM65X_IOPAD(0x01d4, PIN_OUTPUT, 7) /* (AG12) GPIO1_21 */ /* RS232-TX-LED */ + AM65X_IOPAD(0x0234, PIN_OUTPUT, 7) /* (AD28) GPIO1_45 */ /* RS232-RX-LED */ + AM65X_IOPAD(0x0238, PIN_OUTPUT, 7) /* (U26) GPIO1_46 */ /* RS485-RX-LED */ + AM65X_IOPAD(0x023c, PIN_OUTPUT, 7) /* (V25) GPIO1_47 */ /* SD-CARD-READY-LED */ + AM65X_IOPAD(0x0240, PIN_OUTPUT, 7) /* (U24) GPIO1_48 */ /* BUSFAULT-LED */ + AM65X_IOPAD(0x0298, PIN_OUTPUT, 7) /* (AE28) GPIO1_70 */ /* ERROR-LED */ >; }; - main_spi0_pins_default: main-spi0-pins-default { + gpio0_pins_default: gpio0_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (R28) GPIO0_16 */ /*ETH1-PHY-RESET*/ + AM65X_IOPAD(0x0058, PIN_INPUT, 7) /* (R26) GPIO0_22 */ /*RUN/STOP SW*/ + AM65X_IOPAD(0x0060, PIN_OUTPUT, 7) /* (T25) GPIO0_24 */ /*/AX58100-RST*/ + AM65X_IOPAD(0x0064, PIN_OUTPUT, 7) /* (T24) GPIO0_25 */ /*/AX58100-PYH-RST*/ + AM65X_IOPAD(0x0068, PIN_OUTPUT, 7) /* (R24) GPIO0_26 */ /*CAN-TERM*/ + AM65X_IOPAD(0x0070, PIN_OUTPUT, 7) /* (R25) GPIO0_28 */ /*GPIO-eMMC-RST*/ + AM65X_IOPAD(0x0074, PIN_INPUT, 7) /* (T27) GPIO0_29 */ /*/24V-LV*/ + AM65X_IOPAD(0x00ac, PIN_INPUT, 1) /* (AH15) PRG2_PRU1_GPO0.GPIO0_43 */ + AM65X_IOPAD(0x00b0, PIN_INPUT, 1) /* (AC16) PRG2_PRU1_GPO1.GPIO0_44 */ + AM65X_IOPAD(0x00b4, PIN_INPUT, 1) /* (AD17) PRG2_PRU1_GPO2.GPIO0_45 */ + AM65X_IOPAD(0x00b8, PIN_INPUT, 1) /* (AH14) PRG2_PRU1_GPO3.GPIO0_46 */ + AM65X_IOPAD(0x00d8, PIN_INPUT, 1) /* (AD14) PRG2_PRU1_GPO16.GPIO0_55 */ /*HS_PRU2_LV*/ + AM65X_IOPAD(0x00f4, PIN_INPUT, 7) /* (AF27) GPIO0_61 */ /*PRU-IRQ*/ + AM65X_IOPAD(0x0108, PIN_OUTPUT, 7) /* (AH25) GPIO0_66 */ /*ETH0-PHY-RESET*/ + AM65X_IOPAD(0x0124, PIN_OUTPUT, 7) /* (AH26) GPIO0_73 */ /*ECAT2-PHY-RST*/ + >; + }; + + ledgpio0_pins_default: ledgpio0_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ - AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ - AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */ - AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ + AM65X_IOPAD(0x006c, PIN_OUTPUT | PIN_INPUT, 7) /* (T23) GPIO0_27 */ /* RUN-LED */ >; }; +#if 0 + mygpmc3_pins_default: mygpmc3_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x00bc, PIN_OUTPUT, 3) /* (AG14) PRG2_PRU1_GPO4.GPMC0_A8 */ + AM65X_IOPAD(0x00c0, PIN_OUTPUT, 3) /* (AG15) PRG2_PRU1_GPO5.GPMC0_A7 */ + AM65X_IOPAD(0x00c4, PIN_OUTPUT, 3) /* (AC17) PRG2_PRU1_GPO6.GPMC0_A6 */ + AM65X_IOPAD(0x00cc, PIN_OUTPUT, 3) /* (AD15) PRG2_PRU1_GPO8.GPMC0_A4 */ + AM65X_IOPAD(0x00d0, PIN_OUTPUT, 3) /* (AF14) PRG2_PRU1_GPO9.GPMC0_A3 */ + AM65X_IOPAD(0x00d4, PIN_OUTPUT, 3) /* (AC15) PRG2_PRU1_GPO10.GPMC0_A2 */ + AM65X_IOPAD(0x00d8, PIN_OUTPUT, 3) /* (AD14) PRG2_PRU1_GPO11.GPMC0_A1 */ + AM65X_IOPAD(0x003c, PIN_INPUT, 0) /* (R27) GPMC0_AD15 */ + AM65X_IOPAD(0x0038, PIN_INPUT, 0) /* (P24) GPMC0_AD14 */ + AM65X_IOPAD(0x0034, PIN_INPUT, 0) /* (N25) GPMC0_AD13 */ + AM65X_IOPAD(0x0030, PIN_INPUT, 0) /* (N26) GPMC0_AD12 */ + AM65X_IOPAD(0x002c, PIN_INPUT, 0) /* (P27) GPMC0_AD11 */ + AM65X_IOPAD(0x0028, PIN_INPUT, 0) /* (P28) GPMC0_AD10 */ + AM65X_IOPAD(0x0024, PIN_INPUT, 0) /* (M26) GPMC0_AD9 */ + AM65X_IOPAD(0x0020, PIN_INPUT, 0) /* (N23) GPMC0_AD8 */ + AM65X_IOPAD(0x001c, PIN_INPUT, 0) /* (M25) GPMC0_AD7 */ + AM65X_IOPAD(0x0018, PIN_INPUT, 0) /* (N28) GPMC0_AD6 */ + AM65X_IOPAD(0x0014, PIN_INPUT, 0) /* (N27) GPMC0_AD5 */ + AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) GPMC0_AD4 */ + AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (M24) GPMC0_AD3 */ + AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (M28) GPMC0_AD2 */ + AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (M23) GPMC0_AD1 */ + AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (M27) GPMC0_AD0 */ + AM65X_IOPAD(0x0054, PIN_OUTPUT, 0) /* (P23) GPMC0_BE1n */ + AM65X_IOPAD(0x0048, PIN_OUTPUT, 0) /* (P26) GPMC0_OEn_REn */ + AM65X_IOPAD(0x004c, PIN_OUTPUT, 0) /* (U28) GPMC0_WEn */ + >; + }; +#endif + main_mmc0_pins_default: main-mmc0-pins-default { pinctrl-single,pins = < AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ @@ -307,13 +449,45 @@ >; }; - usb1_pins_default: usb1-pins-default { + icssg1_mdio_pins_default: icssg1_mdio_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18) PRG1_MDIO0_MDIO */ + AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */ + >; + }; + + icssg1_rgmii_pins_default: icssg1_rgmii_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ + AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */ + AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */ + AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */ + AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */ + AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */ + AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + + //ethercat1_pins_default + AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */ + AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */ + AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */ + AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */ + AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20) PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */ + AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19) PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */ + AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19) PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */ + AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19) PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */ + AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */ + AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20) PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */ + AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */ + AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */ >; }; - icssg2_mdio_pins_default: icssg2-mdio-pins-default { + icssg2_mdio_pins_default: icssg2_mdio_pins_default { pinctrl-single,pins = < AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */ AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */ @@ -322,19 +496,6 @@ icssg2_rgmii_pins_default: icssg2-rgmii-pins-default { pinctrl-single,pins = < - AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */ - AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */ - AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */ - AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */ - AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */ - AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */ - AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */ - AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */ - AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */ - AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */ - AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */ - AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */ - AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */ AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */ AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */ @@ -349,9 +510,64 @@ AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */ >; }; + + main_spi0_pins_default: main-spi0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01c4, PIN_OUTPUT, 0) /* (AH13) GPIO1_17 */ /*SPI0-CLK*/ + AM65X_IOPAD(0x01c8, PIN_OUTPUT, 0) /* (AE13) GPIO1_18 */ /*SPI0_D0*/ + AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) GPIO1_19 */ /*SPI0_D1*/ + AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) GPIO1_15 */ /*SPI0_CS0*/ + AM65X_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (AF13) GPIO1_16 */ /*SPI0_CS1*/ + >; + }; + + myspi2_pins_default: myspi2_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (AH12) GPIO1_22 */ /*SPI1_CLK*/ + AM65X_IOPAD(0x01dc, PIN_OUTPUT, 0) /* (AE12) GPIO1_23 */ /*SPI1_D0*/ + AM65X_IOPAD(0x01e0, PIN_INPUT, 0) /* (AF12) GPIO1_24 */ /*SPI1_D1*/ + >; + }; + + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) GPIO1_25 */ /*UART0_RXD*/ + AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) GPIO1_26 */ /*UART0_TXD*/ + >; + }; + + rs232_pins_default: rs232_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0288, PIN_INPUT, 6) /* (Y27) GPIO1_66 */ /*RS232-RXD*/ + AM65X_IOPAD(0x0260, PIN_OUTPUT, 6) /* (W28) GPIO1_56 */ /*RS232-TXD*/ + >; + }; + + rs485_pins_default: rs485_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) GPIO0_93 */ /*RS485-RXD*/ + AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) GPIO0_83 */ /*RS485-TXD*/ + AM65X_IOPAD(0x017c, PIN_OUTPUT_PULLDOWN, 7) /* (AC21) GPIO0_95 */ /*RS485-DIR*/ + >; + }; + + usb0_pins_default: usb0_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) GPIO1_71 */ /*USB0_DRVVBUS*/ + >; + }; + + usb20_host_pins_default: usb20_host_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) GPIO1_72 */ /*USB1_DRVVBUS*/ + >; + }; }; &main_pmx1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_pins_default>; + main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ @@ -366,16 +582,24 @@ >; }; - ecap0_pins_default: ecap0-pins-default { + gpio2_pins_default: gpio2_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ + AM65X_IOPAD(0x0010, PIN_OUTPUT, 7) /* (D21) GPIO1_86 */ /* SER-COMM-EN */ + AM65X_IOPAD(0x0018, PIN_INPUT, 7) /* (B22) GPIO1_88 */ /* DDR-TP0 */ + AM65X_IOPAD(0x001c, PIN_INPUT, 7) /* (C23) GPIO1_89 */ /* DDR-TP1 */ + >; + }; + + ledgpio2_pins_default: ledgpio2_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0014, PIN_OUTPUT, 7) /* (A22) GPIO1_87 */ /* RS485-TX-LED */ >; }; }; &wkup_uart0 { /* Wakeup UART is used by System firmware */ - status = "reserved"; + status = "disabled"; }; &main_uart0 { @@ -384,53 +608,51 @@ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; -&wkup_i2c0 { +//Eric+{ +&main_uart2 { pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - pca9554: gpio@39 { - compatible = "nxp,pca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_pca554_default>; - interrupt-parent = <&wkup_gpio0>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; + power-domains = <&k3_pds 148 TI_SCI_PD_SHARED>; + pinctrl-0 = <&rs232_pins_default>; + status = "okay"; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&rs485_pins_default>; + power-domains = <&k3_pds 147 TI_SCI_PD_SHARED>; + rts-gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rts-delay = <0 0>; + linux,rs485-enabled-at-boot-time; + status = "okay"; }; +//Eric+} &main_i2c0 { + status = "okay"; + pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; + clock-frequency = <100000>; - pca9555: gpio@21 { - compatible = "nxp,pca9555"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; }; }; &main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; -}; + status = "okay"; -&main_i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&main_i2c2_pins_default>; - clock-frequency = <400000>; -}; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <100000>; -&ecap0 { - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins_default>; + s35390a:rtc@30{ + compatible = "sii,s35390a"; + reg = <0x30>; + }; }; &main_spi0 { @@ -451,6 +673,27 @@ }; }; +&main_spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&myspi2_pins_default>; + #address-cells = <1>; + #size-cells= <0>; + ti,pindir-d0-out-d1-in = <1>; + + spidev@0 { + status = "okay"; + //compatible = "fairchild,74hc595"; + compatible = "linux,spidev"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <2>; + registers-default = /bits/ 8 <0xb7>; + spi-max-frequency = <100000>; + }; +}; + &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; @@ -466,26 +709,52 @@ * disable sdhci1 */ &sdhci1 { - vmmc-supply = <&vdd_mmc1_sd>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; }; +&dwc3_1 { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + &usb1 { pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_default>; - dr_mode = "otg"; + pinctrl-0 = <&usb20_host_pins_default>; + dr_mode = "host"; }; &dwc3_0 { - status = "disabled"; + status = "okay"; }; &usb0_phy { - status = "disabled"; + status = "okay"; +}; + +//Eric+{ + +&m_can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcan0_pins_default>; + //stb-gpios = <&main_gpio1 47 GPIO_ACTIVE_HIGH>; + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&usb0 { + pinctrl-names = "default"; + //pinctrl-0 = <&usb0_pins_default>; + dr_mode = "peripheral"; }; +//Eric+} &tscadc0 { adc { @@ -593,74 +862,64 @@ mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; }; -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0{ - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + //Eric- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&phy2ax58100_pins_default &phy2ax58100_mdio2_pins_default>; }; &davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; + reset = <&main_gpio0 25 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; /* PHY datasheet states 1us min */ + + phy0: ethernet-phy@3 { + reg = <3>; }; }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rmii"; phy-handle = <&phy0>; }; -&mcasp0 { - status = "disabled"; -}; - -&mcasp1 { - status = "disabled"; -}; +#if 1 +&icssg1_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_mdio_pins_default>; -&mcasp2 { - status = "disabled"; -}; + //reset = <&main_gpio0 66 GPIO_ACTIVE_LOW>; /*83867*/ + //reset-delay-us = <2>; -&dss { - status = "disabled"; + icssg1_phy0: ethernet-phy@1 { + reg = <1>; + //reset-assert-us = <1000>; + //reset-deassert-us = <1000>; + //reset = <&main_gpio0 25 GPIO_ACTIVE_LOW>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +#if 0 + icssg1_phy1: ethernet-phy@7 { + reg = <7>; + }; +#endif }; +#if 1 &icssg2_mdio { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&icssg2_mdio_pins_default>; - icssg2_phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - }; - - icssg2_phy1: ethernet-phy@3 { - reg = <3>; + //reset = <&main_gpio0 16 GPIO_ACTIVE_LOW>; + //reset-delay-us = <2>; + icssg2_phy2: ethernet-phy@2 { + reg = <2>; ti,rx-internal-delay = ; ti,fifo-depth = ; }; }; +#endif +#endif + diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c index 538232b4c..4485e3ef6 100644 --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c @@ -436,6 +436,9 @@ static const struct usb_device_id blacklist_table[] = { { USB_DEVICE(0x0bda, 0xb009), .driver_info = BTUSB_REALTEK }, { USB_DEVICE(0x2ff8, 0xb011), .driver_info = BTUSB_REALTEK }, + /* Additional Realtek 8761B Bluetooth devices Tp-Link UB500 */ + { USB_DEVICE(0x2357, 0x0604), .driver_info = BTUSB_REALTEK }, + /* Additional Realtek 8821AE Bluetooth devices */ { USB_DEVICE(0x0b05, 0x17dc), .driver_info = BTUSB_REALTEK }, { USB_DEVICE(0x13d3, 0x3414), .driver_info = BTUSB_REALTEK }, diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig index f66ae649b..0ef0eaab3 100644 --- a/drivers/net/ethernet/ti/Kconfig +++ b/drivers/net/ethernet/ti/Kconfig @@ -33,6 +33,7 @@ config TI_DAVINCI_MDIO tristate "TI DaVinci MDIO Support" depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST select PHYLIB + select MDIO_BITBANG help This driver supports TI's DaVinci MDIO module. diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c index a4efd5e35..23f1c24cc 100644 --- a/drivers/net/ethernet/ti/davinci_mdio.c +++ b/drivers/net/ethernet/ti/davinci_mdio.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include /* * This timeout definition is a worst-case ultra defensive measure against @@ -41,6 +43,7 @@ struct davinci_mdio_of_param { int autosuspend_delay_ms; + bool manual_mode; }; struct davinci_mdio_regs { @@ -49,6 +52,15 @@ struct davinci_mdio_regs { #define CONTROL_IDLE BIT(31) #define CONTROL_ENABLE BIT(30) #define CONTROL_MAX_DIV (0xffff) +#define CONTROL_CLKDIV GENMASK(15, 0) + +#define MDIO_MAN_MDCLK_O BIT(2) +#define MDIO_MAN_OE BIT(1) +#define MDIO_MAN_PIN BIT(0) +#define MDIO_MANUALMODE BIT(31) + +#define MDIO_PIN 0 + u32 alive; u32 link; @@ -59,7 +71,9 @@ struct davinci_mdio_regs { u32 userintmasked; u32 userintmaskset; u32 userintmaskclr; - u32 __reserved_1[20]; + u32 manualif; + u32 poll; + u32 __reserved_1[18]; struct { u32 access; @@ -79,6 +93,7 @@ static const struct mdio_platform_data default_pdata = { struct davinci_mdio_data { struct mdio_platform_data pdata; + struct mdiobb_ctrl bb_ctrl; struct davinci_mdio_regs __iomem *regs; struct clk *clk; struct device *dev; @@ -90,6 +105,7 @@ struct davinci_mdio_data { */ bool skip_scan; u32 clk_div; + bool manual_mode; }; static void davinci_mdio_init_clk(struct davinci_mdio_data *data) @@ -128,9 +144,126 @@ static void davinci_mdio_enable(struct davinci_mdio_data *data) writel(data->clk_div | CONTROL_ENABLE, &data->regs->control); } -static int davinci_mdio_reset(struct mii_bus *bus) +static void davinci_mdio_disable(struct davinci_mdio_data *data) +{ + u32 reg; + + /* Disable MDIO state machine */ + reg = readl(&data->regs->control); + + reg &= ~CONTROL_CLKDIV; + reg |= data->clk_div; + + reg &= ~CONTROL_ENABLE; + writel(reg, &data->regs->control); +} + +static void davinci_mdio_enable_manual_mode(struct davinci_mdio_data *data) +{ + u32 reg; + /* set manual mode */ + reg = readl(&data->regs->poll); + reg |= MDIO_MANUALMODE; + writel(reg, &data->regs->poll); +} + +static void davinci_set_mdc(struct mdiobb_ctrl *ctrl, int level) +{ + struct davinci_mdio_data *data; + u32 reg; + + data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl); + reg = readl(&data->regs->manualif); + + if (level) + reg |= MDIO_MAN_MDCLK_O; + else + reg &= ~MDIO_MAN_MDCLK_O; + + writel(reg, &data->regs->manualif); +} + +static void davinci_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) +{ + struct davinci_mdio_data *data; + u32 reg; + + data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl); + reg = readl(&data->regs->manualif); + + if (output) + reg |= MDIO_MAN_OE; + else + reg &= ~MDIO_MAN_OE; + + writel(reg, &data->regs->manualif); +} + +static void davinci_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) +{ + struct davinci_mdio_data *data; + u32 reg; + + data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl); + reg = readl(&data->regs->manualif); + + if (value) + reg |= MDIO_MAN_PIN; + else + reg &= ~MDIO_MAN_PIN; + + writel(reg, &data->regs->manualif); +} + +static int davinci_get_mdio_data(struct mdiobb_ctrl *ctrl) +{ + struct davinci_mdio_data *data; + unsigned long reg; + + data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl); + reg = readl(&data->regs->manualif); + return test_bit(MDIO_PIN, ®); +} + +static int davinci_mdiobb_read(struct mii_bus *bus, int phy, int reg) +{ + int ret; + + ret = pm_runtime_get_sync(bus->parent); + if (ret < 0) { + pm_runtime_put_noidle(bus->parent); + return ret; + } + + ret = mdiobb_read(bus, phy, reg); + + pm_runtime_mark_last_busy(bus->parent); + pm_runtime_put_autosuspend(bus->parent); + + return ret; +} + +static int davinci_mdiobb_write(struct mii_bus *bus, int phy, int reg, + u16 val) +{ + int ret; + + ret = pm_runtime_get_sync(bus->parent); + if (ret < 0) { + pm_runtime_put_noidle(bus->parent); + return ret; + } + + ret = mdiobb_write(bus, phy, reg, val); + + pm_runtime_mark_last_busy(bus->parent); + pm_runtime_put_autosuspend(bus->parent); + + return ret; +} + +static int davinci_mdio_common_reset(struct davinci_mdio_data *data) { - struct davinci_mdio_data *data = bus->priv; u32 phy_mask, ver; int ret; @@ -140,6 +273,11 @@ static int davinci_mdio_reset(struct mii_bus *bus) return ret; } + if (data->manual_mode) { + davinci_mdio_disable(data); + davinci_mdio_enable_manual_mode(data); + } + /* wait for scan logic to settle */ msleep(PHY_MAX_ADDR * data->access_time); @@ -173,6 +311,23 @@ static int davinci_mdio_reset(struct mii_bus *bus) return 0; } +static int davinci_mdio_reset(struct mii_bus *bus) +{ + struct davinci_mdio_data *data = bus->priv; + + return davinci_mdio_common_reset(data); +} + +static int davinci_mdiobb_reset(struct mii_bus *bus) +{ + struct mdiobb_ctrl *ctrl = bus->priv; + struct davinci_mdio_data *data; + + data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl); + + return davinci_mdio_common_reset(data); +} + /* wait until hardware is ready for another user access */ static inline int wait_for_user_access(struct davinci_mdio_data *data) { @@ -226,15 +381,19 @@ static inline int wait_for_idle(struct davinci_mdio_data *data) static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg) { struct davinci_mdio_data *data = bus->priv; - u32 reg; + u32 reg, reg_oldr=0, reg_oldw=0; int ret; if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) + { + printk("davinci_mdio_read phy_id=%d phy_reg=%x return EINVAL\r\n", phy_id, phy_reg); return -EINVAL; + } ret = pm_runtime_get_sync(data->dev); if (ret < 0) { pm_runtime_put_noidle(data->dev); + printk("davinci_mdio_read phy_id=%d phy_reg=%x pm_runtime_get_sync ret=%x\r\n", phy_id, phy_reg, ret); return ret; } @@ -246,21 +405,34 @@ static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg) if (ret == -EAGAIN) continue; if (ret < 0) + { + printk("davinci_mdio_read phy_id=%d phy_reg=%x wait_for_user_access[1] ret=%x\r\n", phy_id, phy_reg, ret); break; + } writel(reg, &data->regs->user[0].access); + reg_oldw = reg; ret = wait_for_user_access(data); if (ret == -EAGAIN) continue; if (ret < 0) + { + printk("davinci_mdio_read phy_id=%d phy_reg=%x wait_for_user_access[2] ret=%x\r\n", phy_id, phy_reg, ret); break; + } reg = readl(&data->regs->user[0].access); + reg_oldr = reg; ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO; break; } + if (phy_id == 1) + { + printk("davinci_mdio_read phy_id=%d phy_reg=%x reg_oldw=%x reg_oldr=%x reg=%x ret=%x\r\n", phy_id, phy_reg, reg_oldw, reg_oldr, reg, ret); + } + pm_runtime_mark_last_busy(data->dev); pm_runtime_put_autosuspend(data->dev); return ret; @@ -324,6 +496,28 @@ static int davinci_mdio_probe_dt(struct mdio_platform_data *data, return 0; } +struct k3_mdio_soc_data { + bool manual_mode; +}; + +static const struct k3_mdio_soc_data am65_mdio_soc_data = { + .manual_mode = true, +}; + +static const struct soc_device_attribute k3_mdio_socinfo[] = { + { .family = "AM62X", .revision = "SR1.0", .data = &am65_mdio_soc_data }, + { .family = "AM64X", .revision = "SR1.0", .data = &am65_mdio_soc_data }, + { .family = "AM64X", .revision = "SR2.0", .data = &am65_mdio_soc_data }, + { .family = "AM65X", .revision = "SR1.0", .data = &am65_mdio_soc_data }, + { .family = "AM65X", .revision = "SR2.0", .data = &am65_mdio_soc_data }, + { .family = "J7200", .revision = "SR1.0", .data = &am65_mdio_soc_data }, + { .family = "J7200", .revision = "SR2.0", .data = &am65_mdio_soc_data }, + { .family = "J721E", .revision = "SR1.0", .data = &am65_mdio_soc_data }, + { .family = "J721E", .revision = "SR2.0", .data = &am65_mdio_soc_data }, + { .family = "J721S2", .revision = "SR1.0", .data = &am65_mdio_soc_data}, + { /* sentinel */ }, +}; + #if IS_ENABLED(CONFIG_OF) static const struct davinci_mdio_of_param of_cpsw_mdio_data = { .autosuspend_delay_ms = 100, @@ -337,6 +531,14 @@ static const struct of_device_id davinci_mdio_of_mtable[] = { MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable); #endif +static const struct mdiobb_ops davinci_mdiobb_ops = { + .owner = THIS_MODULE, + .set_mdc = davinci_set_mdc, + .set_mdio_dir = davinci_set_mdio_dir, + .set_mdio_data = davinci_set_mdio_data, + .get_mdio_data = davinci_get_mdio_data, +}; + static int davinci_mdio_probe(struct platform_device *pdev) { struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev); @@ -351,7 +553,26 @@ static int davinci_mdio_probe(struct platform_device *pdev) if (!data) return -ENOMEM; - data->bus = devm_mdiobus_alloc(dev); + data->manual_mode = false; + data->bb_ctrl.ops = &davinci_mdiobb_ops; + + if (IS_ENABLED(CONFIG_OF) && dev->of_node) { + const struct soc_device_attribute *soc_match_data; + + soc_match_data = soc_device_match(k3_mdio_socinfo); + if (soc_match_data && soc_match_data->data) { + const struct k3_mdio_soc_data *socdata = + soc_match_data->data; + + data->manual_mode = socdata->manual_mode; + } + } + + if (data->manual_mode) + data->bus = alloc_mdio_bitbang(&data->bb_ctrl); + else + data->bus = devm_mdiobus_alloc(dev); + if (!data->bus) { dev_err(dev, "failed to alloc mii bus\n"); return -ENOMEM; @@ -377,11 +598,20 @@ static int davinci_mdio_probe(struct platform_device *pdev) } data->bus->name = dev_name(dev); - data->bus->read = davinci_mdio_read; - data->bus->write = davinci_mdio_write; - data->bus->reset = davinci_mdio_reset; + + if (data->manual_mode) { + data->bus->read = davinci_mdiobb_read; + data->bus->write = davinci_mdiobb_write; + data->bus->reset = davinci_mdiobb_reset; + + dev_info(dev, "Configuring MDIO in manual mode\n"); + } else { + data->bus->read = davinci_mdio_read; + data->bus->write = davinci_mdio_write; + data->bus->reset = davinci_mdio_reset; + data->bus->priv = data; + } data->bus->parent = dev; - data->bus->priv = data; data->clk = devm_clk_get(dev, "fck"); if (IS_ERR(data->clk)) { @@ -439,9 +669,13 @@ static int davinci_mdio_remove(struct platform_device *pdev) { struct davinci_mdio_data *data = platform_get_drvdata(pdev); - if (data->bus) + if (data->bus) { mdiobus_unregister(data->bus); + if (data->manual_mode) + free_mdio_bitbang(data->bus); + } + pm_runtime_dont_use_autosuspend(&pdev->dev); pm_runtime_disable(&pdev->dev); @@ -458,7 +692,9 @@ static int davinci_mdio_runtime_suspend(struct device *dev) ctrl = readl(&data->regs->control); ctrl &= ~CONTROL_ENABLE; writel(ctrl, &data->regs->control); - wait_for_idle(data); + + if (!data->manual_mode) + wait_for_idle(data); return 0; } @@ -467,7 +703,12 @@ static int davinci_mdio_runtime_resume(struct device *dev) { struct davinci_mdio_data *data = dev_get_drvdata(dev); - davinci_mdio_enable(data); + if (data->manual_mode) { + davinci_mdio_disable(data); + davinci_mdio_enable_manual_mode(data); + } else { + davinci_mdio_enable(data); + } return 0; } #endif diff --git a/drivers/net/mdio/mdio-bitbang.c b/drivers/net/mdio/mdio-bitbang.c index 5136275c8..d3915f831 100644 --- a/drivers/net/mdio/mdio-bitbang.c +++ b/drivers/net/mdio/mdio-bitbang.c @@ -149,7 +149,7 @@ static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, u32 addr) return dev_addr; } -static int mdiobb_read(struct mii_bus *bus, int phy, int reg) +int mdiobb_read(struct mii_bus *bus, int phy, int reg) { struct mdiobb_ctrl *ctrl = bus->priv; int ret, i; @@ -180,8 +180,9 @@ static int mdiobb_read(struct mii_bus *bus, int phy, int reg) mdiobb_get_bit(ctrl); return ret; } +EXPORT_SYMBOL(mdiobb_read); -static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) +int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) { struct mdiobb_ctrl *ctrl = bus->priv; @@ -201,6 +202,7 @@ static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) mdiobb_get_bit(ctrl); return 0; } +EXPORT_SYMBOL(mdiobb_write); struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl) { diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index d2f6d8107..12eb12c91 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -2192,7 +2192,10 @@ int genphy_update_link(struct phy_device *phydev) bmcr = phy_read(phydev, MII_BMCR); if (bmcr < 0) + { + printk("genphy_update_link phy_read addr=%d MII_BMCR = 0x%x\r\n", phydev->mdio.addr, bmcr); return bmcr; + } /* Autoneg is being started, therefore disregard BMSR value and * report link as down. @@ -2208,7 +2211,10 @@ int genphy_update_link(struct phy_device *phydev) if (!phy_polling_mode(phydev) || !phydev->link) { status = phy_read(phydev, MII_BMSR); if (status < 0) + { + printk("genphy_update_link phy_read addr=%d MII_BMSR = 0x%x\r\n", phydev->mdio.addr, status); return status; + } else if (status & BMSR_LSTATUS) goto done; } @@ -2216,7 +2222,10 @@ int genphy_update_link(struct phy_device *phydev) /* Read link and autonegotiation status */ status = phy_read(phydev, MII_BMSR); if (status < 0) + { + printk("genphy_update_link phy_read addr=%dMII_BMSR[2] = 0x%x\r\n", phydev->mdio.addr, status); return status; + } done: phydev->link = status & BMSR_LSTATUS ? 1 : 0; phydev->autoneg_complete = status & BMSR_ANEGCOMPLETE ? 1 : 0; diff --git a/include/linux/mdio-bitbang.h b/include/linux/mdio-bitbang.h index 5d71e8a85..aca4dc037 100644 --- a/include/linux/mdio-bitbang.h +++ b/include/linux/mdio-bitbang.h @@ -35,6 +35,9 @@ struct mdiobb_ctrl { const struct mdiobb_ops *ops; }; +int mdiobb_read(struct mii_bus *bus, int phy, int reg); +int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val); + /* The returned bus is not yet registered with the phy layer. */ struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl);