/dts-v1/;

#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"

/ {
	model = "TI AM335x BeagleBone Black";
	compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
};

&am33xx_pinmux {
        bb_lcd_pwm_backlight_pins: pinmux_bb_lcd_pwm_backlight_pins {
	        pinctrl-single,pins = <
	                0x48 0x06       /* gpmc_a2.ehrpwm1a, OMAP_MUX_MODE6 | AM33XX_PIN_OUTPUT */
		>;
	};
									

        lcd_pins: lcd_pins {
		pinctrl-single,pins = <
			0xa0 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data0 */
			0xa4 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data1 */
			0xa8 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data2 */
			0xac (PIN_OUTPUT | MUX_MODE0)            /* lcd_data3 */
			0xb0 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data4 */
			0xb4 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data5 */
			0xb8 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data6 */
			0xbc (PIN_OUTPUT | MUX_MODE0)            /* lcd_data7 */
			0xc0 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data8 */
			0xc4 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data9 */
			0xc8 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data10 */
			0xcc (PIN_OUTPUT | MUX_MODE0)            /* lcd_data11 */
			0xd0 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data12 */
			0xd4 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data13 */
			0xd8 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data14 */
			0xdc (PIN_OUTPUT | MUX_MODE0)            /* lcd_data15 */
			0x3c (PIN_OUTPUT | MUX_MODE0)            /* lcd_data16 */
			0x38 (PIN_OUTPUT | MUX_MODE0)            /* lcd_data17 */
			0xe0 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)   /* lcd_vsync */
			0xe4 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)   /* lcd_hsync */
			0xe8 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)   /* lcd_pclk */
			0xec (PIN_OUTPUT_PULLDOWN | MUX_MODE0)   /* lcd_ac_bias_en */
		>;
	};
	spi0_pins: spi0_pins {
	        pinctrl-single,pins = <
		        0x150 (PIN_INPUT_PULLUP | MUX_MODE0)    /* P9.22, spi0_sclk */
			0x154 (PIN_INPUT_PULLUP | MUX_MODE0)    /* P9.21, spi0_d0 (miso) */
			0x158 (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* P9.18, spi0_d1 (mosi) */
			0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* P9.17, spi0_cs0 */
		>;
	};
	lcdreset_pins: lcdreset_pins {
	        pinctrl-single,pins = <
			0x78 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* P9.12, gpio1_28 reset */
		>;
	};
};

&spi0 {
        #address-cells = <1>;
        #size-cells = <0>;
	
        status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>;

	panel@0 {
		compatible = "sitronix,st7789v";
		reg = <0>;
		reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
		spi-max-frequency = <100000>;
		spi-cpol;
		spi-cpha;
	};
};

&lcdc {
	status = "okay";
};

&sgx {
	status = "okay";
};

&epwmss1 {
        status = "okay";
};

&ehrpwm1 {
        pinctrl-names = "default";
	pinctrl-0 = <&bb_lcd_pwm_backlight_pins>;
	status = "okay";
};
			

/ {


	lcd0: display {
		status = "okay";
		compatible = "ti,tilcdc,panel";
		label = "lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&lcd_pins>;

		panel-info {
			ac-bias           = <255>;
			ac-bias-intrpt    = <0>;
			dma-burst-sz      = <16>;
			bpp               = <24>;
			fdd               = <0x80>;
			sync-edge         = <0>;
			sync-ctrl         = <1>;
			raster-order      = <0>;
			fifo-th           = <0>;
		};

		display-timings {
			native-mode = <&timing0>;
			timing0: 320x240 {
				clock-frequency = <9200000>;
				hactive = <320>;
				vactive = <240>;
				hfront-porch = <8>;
				hback-porch = <7>;
				hsync-len = <8>;
				vback-porch = <2>;
				vfront-porch = <3>;
				vsync-len = <4>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};
	};

        fb {
		compatible = "ti,am33xx-tilcdc";
		reg = <0x4830e000 0x1000>;
		interrupt-parent = <&intc>;
		interrupts = <36>;
		ti,hwmods = "lcdc";
	};

        backlight {
                status = "okay";
                compatible = "pwm-backlight";
                pwms = <&ehrpwm1 0 500000>;
                brightness-levels = <
                        0  1  2  3  4  5  6  7  8  9
                        10 11 12 13 14 15 16 17 18 19
                        20 21 22 23 24 25 26 27 28 29
                        30 31 32 33 34 35 36 37 38 39
                        40 41 42 43 44 45 46 47 48 49
                        50 51 52 53 54 55 56 57 58 59
                        60 61 62 63 64 65 66 67 68 69
                        70 71 72 73 74 75 76 77 78 79
                        80 81 82 83 84 85 86 87 88 89
                        90 91 92 93 94 95 96 97 98 99
                        100
                >;
                default-brightness-level = <100>;
        };

};

&ldo3_reg {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
};

&mmc1 {
	vmmc-supply = <&vmmcsd_fixed>;
};

&mmc2 {
	vmmc-supply = <&vmmcsd_fixed>;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_pins>;
	bus-width = <8>;
	status = "okay";
};

&cpu0_opp_table {
	/*
	 * All PG 2.0 silicon may not support 1GHz but some of the early
	 * BeagleBone Blacks have PG 2.0 silicon which is guaranteed
	 * to support 1GHz OPP so enable it for PG 2.0 on this board.
	 */
	oppnitro@1000000000 {
		opp-supported-hw = <0x06 0x0100>;
	};
};

&rtc {
	system-power-controller;
};