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B:AMC-D24A4-RF4 (c) CommAgility Ltd.
D:1 PRODTEST V1.1.0 Feb 23 2016 17:14:58

K7:0x24a4 IMG:0x0005 GLUE:0x0003

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Active connection : 10.10.12.20:51199

CA> dspteststart 1 0x51 1 1
Test command 0x0051 sent to CORE 1
CA> dsptestdump 1 1
CAD1:Performing Card Init
Waiting for Test Command
HYP_slavetest:DSP:1:
HYP_slavetest:DSP:1: Pass Running Hyperlink at 10G
HYP_slavetest:DSP:1: Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01
.05:Nov 19 2012:16:04:15
HYP_slavetest:DSP:1:About to do system setup (PLL, PSC, and DDR)
HYP_slavetest:DSP 1:
&&
CA> dsptestdump 1 1
CAD1:HYP_slavetest:DSP 1: Constructed SERDES configs: PLL=0x00000040; RX=0x0046c
485; TX=0x000d2b05
HYP_slavetest:DSP:1: system setup worked
HYP_slavetest:DSP:1: About to set up HyperLink Peripheral
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: ======== begin registers before initialization ========
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Revision register contents:
  Raw    = 0x4e901900
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Status register contents:
  Raw        = 0x04400005
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Link status register contents:
  Raw       = 0xfdf0bdfa
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Control register contents:
  Raw             = 0x00000000
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Control register contents:
  Raw        = 0x0000000&&
CA> dsptestdump 1 1
CAD1:0
HYP_slavetest:DSP 1: ========= end registers before initialization =======
HYP_mastertest:DSP:1: Checking for Corrected and Non-corrected errors
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: SERDES_STS (32 bits) contents: 0x0c183061; lock = 1
HYP_slavetest:DSP 1: ====== begin registers after initialization =======
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Status register contents:
  Raw        = 0x04400005
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Link status register contents:
  Raw       = 0xfdf0bdfa
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Control register contents:
  Raw             = 0x00006200
HYP_slavetest:DSP 1: ===== end registers after initialization ======
HYP_slavetest:DSP 1: Waiting 5 seconds to check link stability
HYP_mastertest:DSP:1: Checking&&
CA> dsptestdump 1 1
CAD1: for Corrected and Non-corrected errors
HYP_mastertest:DSP:1: Checking for Corrected and Non-corrected errors
HYP_slavetest:DSP 1: Link seems stable
HYP_slavetest:DSP 1: About to try to read remote registers
HYP_mastertest:DSP:1: Checking for Corrected and Non-corrected errors
HYP_slavetest:DSP 1: ======== begin REMOTE registers after initialization ======
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Status register contents:
  Raw        = 0x0440000b
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Link status register contents:
  Raw       = 0xfdf0bdf3
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Control register contents:
  Raw             = 0x00006200
HYP_slavetest:DSP 1: ======== end REMOTE registers after initialization ======
HYP_slavetest:DSP:1: Running at 10G
HY&&
CA> dsptestdump 1 1
CAD1:P_slavetest:DSP:1: Link Speed is 4 * 10.0 Gbps
HYP_slavetest:DSP:1: Peripheral setup worked
hyplnkExampleAddrMap:DSP 1:
&&
CA> dsptestdump 1 1
Nothing to dump, testlog empty
CA> dsptestdump 1 1
Nothing to dump, testlog empty
CA> mr 0x21400000 10
0x21400000 -> 0x4e901900
0x21400004 -> 0x00006200
0x21400008 -> 0x04400005
0x2140000c -> 0x80000000
0x21400010 -> 0x00000000
0x21400014 -> 0x00000000
0x21400018 -> 0x00000000
0x2140001c -> 0x00000c0b
0x21400020 -> 0x00000000
0x21400024 -> 0x00000000
0x21400028 -> 0x00000000
0x2140002c -> 0x00000c06
0x21400030 -> 0x00000000
0x21400034 -> 0x00000000
0x21400038 -> 0x00000000
0x2140003c -> 0x11800015
CA> mr 0x21400040 10
0x21400040 -> 0x0001009e
0x21400044 -> 0x0707000c
0x21400048 -> 0x00000000
0x2140004c -> 0x00000000
0x21400050 -> 0x00000000
0x21400054 -> 0x00000000
0x21400058 -> 0xfdf0bdfa
0x2140005c -> 0x00000000
0x21400060 -> 0x00000000
0x21400064 -> 0x00000000
0x21400068 -> 0x00000000
0x2140006c -> 0x00000000
0x21400070 -> 0xffff0000
0x21400074 -> 0x00000000
0x21400078 -> 0x00000000
0x2140007c -> 0x00000000
CA>