- CORE -
internal clk count		6
dss_ick        	100000000	2
dss1_alwon_fck 	96000000	2
dss2_alwon_fck 	13000000	2
dss_tv_fck     	54000000	0
dss_96m_fck    	96000000	0
- DSS -
dpll4_ck 864000000
dss1_alwon_fclk = 864000000 / 9  = 96000000
- DISPC -
dispc fclk source = dsi1_pll_fclk
fck		120000000       
lck		120000000       lck div	1
pck		30000000        pck div	4
- DSI PLL -
dsi pll source = dss2_alwon_fclk
Fint		1000000         regn 13
CLKIN4DDR	720000000       regm 360
dsi1_pll_fck	120000000       regm3 6	(on)
dsi2_pll_fck	120000000       regm4 6	(on)
- DSI -
dsi fclk source = dsi2_pll_fclk
DSI_FCLK	120000000
DDR_CLK		180000000
TxByteClkHS	45000000
LP_CLK		7500000
VP_CLK		120000000
VP_PCLK		30000000