#
# J-LINK GDB SERVER Configuration file
#
# Set the listening port of GDB Server to tcp port 2331
target remote localhost:2331
monitor reset
set language c

#****************************************************
# Convenience variables
# 
# GDB provides convenience variables that you can use within GDB to hold on to a value and refer to it later. 
# These variables exist entirely within GDB; they are not part of your program, and setting a convenience variable has no direct effect on further execution of your program. That is why you can use them freely. 
# 
# Convenience variables are prefixed with `$'. Any name preceded by `$' can be used for a convenience variable, unless it is one of the predefined machine-specific register names (see section Registers). 
# (Value history references, in contrast, are numbers preceded by `$'. See section Value history.) 
#****************************************************

#****************************************************
#PRCM module definitions
#****************************************************
set $PRCM_BASE_ADDR                    = 0x44E00000
set $CM_PER_EMIF_CLKCTRL               = ($PRCM_BASE_ADDR + 0x028)
set $CM_PER_EMIF_FW_CLKCTRL            = ($PRCM_BASE_ADDR + 0x0D0)

set $CM_WKUP_CLKSTCTRL                 = ($PRCM_BASE_ADDR + 0x400)
set $CM_WKUP_GPIO0_CLKCTRL             = ($PRCM_BASE_ADDR + 0x408)
set $CM_AUTOIDLE_DPLL_MPU              = ($PRCM_BASE_ADDR + 0x41C)
set $CM_IDLEST_DPLL_MPU                = ($PRCM_BASE_ADDR + 0x420)
set $CM_CLKSEL_DPLL_MPU                = ($PRCM_BASE_ADDR + 0x42C)
set $CM_AUTOIDLE_DPLL_DDR              = ($PRCM_BASE_ADDR + 0x430)
set $CM_IDLEST_DPLL_DDR                = ($PRCM_BASE_ADDR + 0x434)
set $CM_CLKSEL_DPLL_DDR                = ($PRCM_BASE_ADDR + 0x440)
set $CM_AUTOIDLE_DPLL_DISP             = ($PRCM_BASE_ADDR + 0x444)
set $CM_IDLEST_DPLL_DISP               = ($PRCM_BASE_ADDR + 0x448)
set $CM_CLKSEL_DPLL_DISP               = ($PRCM_BASE_ADDR + 0x454)
set $CM_AUTOIDLE_DPLL_CORE             = ($PRCM_BASE_ADDR + 0x458)
set $CM_IDLEST_DPLL_CORE               = ($PRCM_BASE_ADDR + 0x45C)
set $CM_CLKSEL_DPLL_CORE               = ($PRCM_BASE_ADDR + 0x468)
set $CM_AUTOIDLE_DPLL_PER              = ($PRCM_BASE_ADDR + 0x46C)
set $CM_IDLEST_DPLL_PER                = ($PRCM_BASE_ADDR + 0x470)
set $CM_CLKSEL_DPLL_PER                = ($PRCM_BASE_ADDR + 0x49C)

set $CM_DIV_M4_DPLL_CORE               = ($PRCM_BASE_ADDR + 0x480)
set $CM_DIV_M5_DPLL_CORE               = ($PRCM_BASE_ADDR + 0x484)
set $CM_CLKMODE_DPLL_MPU               = ($PRCM_BASE_ADDR + 0x488)
set $CM_CLKMODE_DPLL_PER               = ($PRCM_BASE_ADDR + 0x48C)
set $CM_CLKMODE_DPLL_CORE              = ($PRCM_BASE_ADDR + 0x490)
set $CM_CLKMODE_DPLL_DDR               = ($PRCM_BASE_ADDR + 0x494)
set $CM_CLKMODE_DPLL_DISP              = ($PRCM_BASE_ADDR + 0x498)

set $CM_DIV_M2_DPLL_DDR                = ($PRCM_BASE_ADDR + 0x4A0)
set $CM_DIV_M2_DPLL_DISP               = ($PRCM_BASE_ADDR + 0x4A4)
set $CM_DIV_M2_DPLL_MPU                = ($PRCM_BASE_ADDR + 0x4A8)
set $CM_DIV_M2_DPLL_PER                = ($PRCM_BASE_ADDR + 0x4AC)
set $CM_DIV_M6_DPLL_CORE               = ($PRCM_BASE_ADDR + 0x4D8)

set $CM_CLKOUT_CTRL                    = ($PRCM_BASE_ADDR + 0x700)

#****************************************************
#Control module definitions
#****************************************************

set $CONTROL_BASE_ADDR       = 0x44E10000

set $CONTROL_STATUS          = ($CONTROL_BASE_ADDR + 0x40)
set $CONF_XDMA_EVENT_INTR1   = ($CONTROL_BASE_ADDR + 0x9b4)

set $CONTROL_CONF_USB0_DRVVBUS    = ($CONTROL_BASE_ADDR + 0x0a1c)

#DDR IO Control Registers
set $DDR_IO_CTRL             = ($CONTROL_BASE_ADDR + 0x0E04) 
set $VTP_CTRL_REG            = ($CONTROL_BASE_ADDR + 0x0E0C) 
set $DDR_CKE_CTRL            = ($CONTROL_BASE_ADDR + 0x131C)
set $DDR_CMD0_IOCTRL         = ($CONTROL_BASE_ADDR + 0x1404)
set $DDR_CMD1_IOCTRL         = ($CONTROL_BASE_ADDR + 0x1408)
set $DDR_CMD2_IOCTRL         = ($CONTROL_BASE_ADDR + 0x140C)
set $DDR_DATA0_IOCTRL        = ($CONTROL_BASE_ADDR + 0x1440)
set $DDR_DATA1_IOCTRL        = ($CONTROL_BASE_ADDR + 0x1444)

#****************************************************
#GPIO module definitions
#****************************************************

set $GPIO0_BASE_ADDR         = 0x44E07000
set $GPIO0_SYSCONFIG          = ($GPIO0_BASE_ADDR + 0x10)
set $GPIO0_SYSSTATUS          = ($GPIO0_BASE_ADDR + 0x114)
set $GPIO0_CTRL               = ($GPIO0_BASE_ADDR + 0x130)
set $GPIO0_OE                 = ($GPIO0_BASE_ADDR + 0x134)
set $GPIO0_CLEARDATAOUT       = ($GPIO0_BASE_ADDR + 0x190)
set $GPIO0_SETDATAOUT         = ($GPIO0_BASE_ADDR + 0x194)

#********************************************************************
#EMIF4DC module definitions
#********************************************************************
set $EMIF_BASE_ADDR                    = 0x4C000000
set $EMIF_STATUS_REG                   = ($EMIF_BASE_ADDR + 0x004)
set $EMIF_SDRAM_CONFIG_REG             = ($EMIF_BASE_ADDR + 0x008)
set $EMIF_SDRAM_CONFIG_2_REG           = ($EMIF_BASE_ADDR + 0x00C)
set $EMIF_SDRAM_REF_CTRL_REG           = ($EMIF_BASE_ADDR + 0x010)
set $EMIF_SDRAM_REF_CTRL_SHDW_REG      = ($EMIF_BASE_ADDR + 0x014)
set $EMIF_SDRAM_TIM_1_REG              = ($EMIF_BASE_ADDR + 0x018)
set $EMIF_SDRAM_TIM_1_SHDW_REG         = ($EMIF_BASE_ADDR + 0x01C)
set $EMIF_SDRAM_TIM_2_REG              = ($EMIF_BASE_ADDR + 0x020)
set $EMIF_SDRAM_TIM_2_SHDW_REG         = ($EMIF_BASE_ADDR + 0x024)
set $EMIF_SDRAM_TIM_3_REG              = ($EMIF_BASE_ADDR + 0x028)
set $EMIF_SDRAM_TIM_3_SHDW_REG         = ($EMIF_BASE_ADDR + 0x02C)
set $EMIF_LPDDR2_NVM_TIM_REG           = ($EMIF_BASE_ADDR + 0x030)
set $EMIF_LPDDR2_NVM_TIM_SHDW_REG      = ($EMIF_BASE_ADDR + 0x034)
set $EMIF_PWR_MGMT_CTRL_REG            = ($EMIF_BASE_ADDR + 0x038)
set $EMIF_PWR_MGMT_CTRL_SHDW_REG       = ($EMIF_BASE_ADDR + 0x03C)
set $EMIF_LPDDR2_MODE_REG_DATA_REG     = ($EMIF_BASE_ADDR + 0x040)
set $EMIF_LPDDR2_MODE_REG_CFG_REG      = ($EMIF_BASE_ADDR + 0x050)
set $EMIF_OCP_CONFIG_REG               = ($EMIF_BASE_ADDR + 0x054)
set $EMIF_OCP_CFG_VAL_1_REG            = ($EMIF_BASE_ADDR + 0x058)
set $EMIF_OCP_CFG_VAL_2_REG            = ($EMIF_BASE_ADDR + 0x05C)
set $EMIF_IODFT_TLGC_REG               = ($EMIF_BASE_ADDR + 0x060)
set $EMIF_IODFT_CTRL_MISR_RSLT_REG     = ($EMIF_BASE_ADDR + 0x064)
set $EMIF_IODFT_ADDR_MISR_RSLT_REG     = ($EMIF_BASE_ADDR + 0x068)
set $EMIF_IODFT_DATA_MISR_RSLT_1_REG   = ($EMIF_BASE_ADDR + 0x06C)
set $EMIF_IODFT_DATA_MISR_RSLT_2_REG   = ($EMIF_BASE_ADDR + 0x070)
set $EMIF_IODFT_DATA_MISR_RSLT_3_REG   = ($EMIF_BASE_ADDR + 0x074)
set $EMIF_PERF_CNT_1_REG               = ($EMIF_BASE_ADDR + 0x080)
set $EMIF_PERF_CNT_2_REG               = ($EMIF_BASE_ADDR + 0x084)
set $EMIF_PERF_CNT_CFG_REG             = ($EMIF_BASE_ADDR + 0x088)
set $EMIF_PERF_CNT_SEL_REG             = ($EMIF_BASE_ADDR + 0x08C)
set $EMIF_PERF_CNT_TIM_REG             = ($EMIF_BASE_ADDR + 0x090)
set $EMIF_READ_IDLE_CTRL_REG           = ($EMIF_BASE_ADDR + 0x098)
set $EMIF_READ_IDLE_CTRL_SHDW_REG      = ($EMIF_BASE_ADDR + 0x09C)
set $EMIF_IRQ_EOI_REG                  = ($EMIF_BASE_ADDR + 0x0A0)
set $EMIF_IRQSTATUS_RAW_SYS_REG        = ($EMIF_BASE_ADDR + 0x0A4)
set $EMIF_IRQSTATUS_SYS_REG            = ($EMIF_BASE_ADDR + 0x0AC)
set $EMIF_IRQENABLE_SET_SYS_REG        = ($EMIF_BASE_ADDR + 0x0B4)
set $EMIF_IRQENABLE_CLR_SYS_REG        = ($EMIF_BASE_ADDR + 0x0BC)
set $EMIF_ZQ_CONFIG_REG                = ($EMIF_BASE_ADDR + 0x0C8)
set $EMIF_TEMP_ALERT_CONFIG_REG        = ($EMIF_BASE_ADDR + 0x0CC)
set $EMIF_OCP_ERR_LOG_REG              = ($EMIF_BASE_ADDR + 0x0D0)
set $EMIF_RDWR_LVL_RMP_WIN_REG         = ($EMIF_BASE_ADDR + 0x0D4)
set $EMIF_RDWR_LVL_RMP_CTRL_REG        = ($EMIF_BASE_ADDR + 0x0D8)
set $EMIF_RDWR_LVL_CTRL_REG            = ($EMIF_BASE_ADDR + 0x0DC)
set $EMIF_DDR_PHY_CTRL_1_REG           = ($EMIF_BASE_ADDR + 0x0E4)
set $EMIF_DDR_PHY_CTRL_1_SHDW_REG      = ($EMIF_BASE_ADDR + 0x0E8)
set $EMIF_DDR_PHY_CTRL_2_REG           = ($EMIF_BASE_ADDR + 0x0EC)
set $EMIF_PRI_COS_MAP_REG              = ($EMIF_BASE_ADDR + 0x100)
set $EMIF_CONNID_COS_1_MAP_REG         = ($EMIF_BASE_ADDR + 0x104)
set $EMIF_CONNID_COS_2_MAP_REG         = ($EMIF_BASE_ADDR + 0x108)
set $EMIF_RD_WR_EXEC_THRSH_REG         = ($EMIF_BASE_ADDR + 0x120)


#*******************************************************************
#DDR PHY registers
#*******************************************************************
set $DDR_PHY_BASE_ADDR                                   = 0x44E12000

#CMD0									
set	$CMD0_REG_PHY_CTRL_SLAVE_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x01C)	
set	$CMD0_REG_PHY_CTRL_SLAVE_FORCE_0                     = ($DDR_PHY_BASE_ADDR + 0x020)	
set	$CMD0_REG_PHY_CTRL_SLAVE_DELAY_0                     = ($DDR_PHY_BASE_ADDR + 0x024)	
set	$CMD0_REG_PHY_DLL_LOCK_DIFF_0                     = ($DDR_PHY_BASE_ADDR + 0x028)	
set	$CMD0_REG_PHY_INVERT_CLKOUT_0                     = ($DDR_PHY_BASE_ADDR + 0x02C)	
set	$CMD0_PHY_REG_STATUS_PHY_CTRL_DLL_LOCK_0                     = ($DDR_PHY_BASE_ADDR + 0x030)	
set	$CMD0_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE_0                     = ($DDR_PHY_BASE_ADDR + 0x034)	
set	$CMD0_PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE_0                     = ($DDR_PHY_BASE_ADDR + 0x038)	
set	$CMD0_PHY_REG_STATUS_PHY_CTRL_OF_OUT_DELAY_VALUE_0                     = ($DDR_PHY_BASE_ADDR + 0x03C)	
									
#CMD1									
set	$CMD1_REG_PHY_CTRL_SLAVE_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x050)	
set	$CMD1_REG_PHY_CTRL_SLAVE_FORCE_0                     = ($DDR_PHY_BASE_ADDR + 0x054)	
set	$CMD1_REG_PHY_CTRL_SLAVE_DELAY_0                     = ($DDR_PHY_BASE_ADDR + 0x058)	
set	$CMD1_REG_PHY_DLL_LOCK_DIFF_0                     = ($DDR_PHY_BASE_ADDR + 0x05C)	
set	$CMD1_REG_PHY_INVERT_CLKOUT_0                     = ($DDR_PHY_BASE_ADDR + 0x060)	
set	$CMD1_PHY_REG_STATUS_PHY_CTRL_DLL_LOCK_0                     = ($DDR_PHY_BASE_ADDR + 0x064)	
set	$CMD1_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE_0                     = ($DDR_PHY_BASE_ADDR + 0x068)	
set	$CMD1_PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE_0                     = ($DDR_PHY_BASE_ADDR + 0x06C)	
set	$CMD1_PHY_REG_STATUS_PHY_CTRL_OF_OUT_DELAY_VALUE_0                     = ($DDR_PHY_BASE_ADDR + 0x070)	
									
#CMD2									
set	$CMD2_REG_PHY_CTRL_SLAVE_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x084)	
set	$CMD2_REG_PHY_CTRL_SLAVE_FORCE_0                     = ($DDR_PHY_BASE_ADDR + 0x088)	
set	$CMD2_REG_PHY_CTRL_SLAVE_DELAY_0                     = ($DDR_PHY_BASE_ADDR + 0x08C)	
set	$CMD2_REG_PHY_DLL_LOCK_DIFF_0                     = ($DDR_PHY_BASE_ADDR + 0x090)	
set	$CMD2_REG_PHY_INVERT_CLKOUT_0                     = ($DDR_PHY_BASE_ADDR + 0x094)	
set	$CMD2_PHY_REG_STATUS_PHY_CTRL_DLL_LOCK_0                     = ($DDR_PHY_BASE_ADDR + 0x098)	
set	$CMD2_PHY_REG_STATUS_PHY_CTRL_OF_IN_LOCK_STATE_0                     = ($DDR_PHY_BASE_ADDR + 0x09C)	
set	$CMD2_PHY_REG_STATUS_PHY_CTRL_OF_IN_DELAY_VALUE_0                     = ($DDR_PHY_BASE_ADDR + 0x0A0)	
set	$CMD2_PHY_REG_STATUS_PHY_CTRL_OF_OUT_DELAY_VALUE_0                     = ($DDR_PHY_BASE_ADDR + 0x0A4)	
									
#DATA0									
set	$DATA0_REG_PHY_DATA_SLICE_IN_USE_0                     = ($DDR_PHY_BASE_ADDR + 0x0B8)	
set	$DATA0_REG_PHY_DIS_CALIB_RST_0                     = ($DDR_PHY_BASE_ADDR + 0x0BC)	
set	$DATA0_REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR_0                     = ($DDR_PHY_BASE_ADDR + 0x0C0)	
set	$DATA0_PHY_RDC_FIFO_RST_ERR_CNT_0                     = ($DDR_PHY_BASE_ADDR + 0x0C4)	
set	$DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x0C8)	
set	$DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x0CC)	
set	$DATA0_REG_PHY_RD_DQS_SLAVE_FORCE_0                     = ($DDR_PHY_BASE_ADDR + 0x0D0)	
set	$DATA0_REG_PHY_RD_DQS_SLAVE_DELAY_0                     = ($DDR_PHY_BASE_ADDR + 0x0D4)	
set	$DATA0_REG_PHY_RD_DQS_SLAVE_DELAY_1                     = ($DDR_PHY_BASE_ADDR + 0x0D8)	
set	$DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x0DC)	
set	$DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x0E0)	
set	$DATA0_REG_PHY_WR_DQS_SLAVE_FORCE_0                     = ($DDR_PHY_BASE_ADDR + 0x0E4)	
set	$DATA0_REG_PHY_WR_DQS_SLAVE_DELAY_0                     = ($DDR_PHY_BASE_ADDR + 0x0E8)	
set	$DATA0_REG_PHY_WR_DQS_SLAVE_DELAY_1                     = ($DDR_PHY_BASE_ADDR + 0x0EC)	
set	$DATA0_REG_PHY_WRLVL_INIT_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x0F0)	
set	$DATA0_REG_PHY_WRLVL_INIT_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x0F4)	
set	$DATA0_REG_PHY_WRLVL_INIT_MODE_0                     = ($DDR_PHY_BASE_ADDR + 0x0F8)	
set	$DATA0_REG_PHY_GATELVL_INIT_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x0FC)	
set	$DATA0_REG_PHY_GATELVL_INIT_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x100)	
set	$DATA0_REG_PHY_GATELVL_INIT_MODE_0                     = ($DDR_PHY_BASE_ADDR + 0x104)	
set	$DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x108)	
set	$DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x10C)	
set	$DATA0_REG_PHY_FIFO_WE_IN_FORCE_0                     = ($DDR_PHY_BASE_ADDR + 0x110)	
set	$DATA0_REG_PHY_FIFO_WE_IN_DELAY_0                     = ($DDR_PHY_BASE_ADDR + 0x114)	
set	$DATA0_REG_PHY_FIFO_WE_IN_DELAY_1                     = ($DDR_PHY_BASE_ADDR + 0x118)	
set	$DATA0_REG_PHY_DQ_OFFSET_0                     = ($DDR_PHY_BASE_ADDR + 0x11C)	
set	$DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x120)	
set	$DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x124)	
set	$DATA0_REG_PHY_WR_DATA_SLAVE_FORCE_0                     = ($DDR_PHY_BASE_ADDR + 0x128)	
set	$DATA0_REG_PHY_WR_DATA_SLAVE_DELAY_0                     = ($DDR_PHY_BASE_ADDR + 0x12C)	
set	$DATA0_REG_PHY_WR_DATA_SLAVE_DELAY_1                     = ($DDR_PHY_BASE_ADDR + 0x130)	
set	$DATA0_REG_PHY_USE_RANK0_DELAYS_0                     = ($DDR_PHY_BASE_ADDR + 0x134)	
set	$DATA0_REG_PHY_DLL_LOCK_DIFF_0                     = ($DDR_PHY_BASE_ADDR + 0x138)	
set	$DATA0_PHY_REG_STATUS_DLL_LOCK_0                     = ($DDR_PHY_BASE_ADDR + 0x13C)	
set	$DATA0_PHY_REG_STATUS_OF_IN_LOCK_STATE_0                     = ($DDR_PHY_BASE_ADDR + 0x140)	
set	$DATA0_PHY_REG_STATUS_OF_IN_DELAY_VALUE_0                     = ($DDR_PHY_BASE_ADDR + 0x144)	
set	$DATA0_PHY_REG_STATUS_OF_OUT_DELAY_VALUE_0                     = ($DDR_PHY_BASE_ADDR + 0x148)	
									
#DATA1									
set	$DATA1_REG_PHY_DATA_SLICE_IN_USE_0                     = ($DDR_PHY_BASE_ADDR + 0x15C)	
set	$DATA1_REG_PHY_DIS_CALIB_RST_0                     = ($DDR_PHY_BASE_ADDR + 0x160)	
set	$DATA1_REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR_0                     = ($DDR_PHY_BASE_ADDR + 0x164)	
set	$DATA1_PHY_RDC_FIFO_RST_ERR_CNT_0                     = ($DDR_PHY_BASE_ADDR + 0x168)	
set	$DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x16C)	
set	$DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x170)	
set	$DATA1_REG_PHY_RD_DQS_SLAVE_FORCE_0                     = ($DDR_PHY_BASE_ADDR + 0x174)	
set	$DATA1_REG_PHY_RD_DQS_SLAVE_DELAY_0                     = ($DDR_PHY_BASE_ADDR + 0x178)	
set	$DATA1_REG_PHY_RD_DQS_SLAVE_DELAY_1                     = ($DDR_PHY_BASE_ADDR + 0x17C)	
set	$DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x180)	
set	$DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x184)	
set	$DATA1_REG_PHY_WR_DQS_SLAVE_FORCE_0                     = ($DDR_PHY_BASE_ADDR + 0x188)	
set	$DATA1_REG_PHY_WR_DQS_SLAVE_DELAY_0                     = ($DDR_PHY_BASE_ADDR + 0x18C)	
set	$DATA1_REG_PHY_WR_DQS_SLAVE_DELAY_1                     = ($DDR_PHY_BASE_ADDR + 0x190)	
set	$DATA1_REG_PHY_WRLVL_INIT_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x194)	
set	$DATA1_REG_PHY_WRLVL_INIT_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x198)	
set	$DATA1_REG_PHY_WRLVL_INIT_MODE_0                     = ($DDR_PHY_BASE_ADDR + 0x19C)	
set	$DATA1_REG_PHY_GATELVL_INIT_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x1A0)	
set	$DATA1_REG_PHY_GATELVL_INIT_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x1A4)	
set	$DATA1_REG_PHY_GATELVL_INIT_MODE_0                     = ($DDR_PHY_BASE_ADDR + 0x1A8)	
set	$DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x1AC)	
set	$DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x1B0)	
set	$DATA1_REG_PHY_FIFO_WE_IN_FORCE_0                     = ($DDR_PHY_BASE_ADDR + 0x1B4)	
set	$DATA1_REG_PHY_FIFO_WE_IN_DELAY_0                     = ($DDR_PHY_BASE_ADDR + 0x1B8)	
set	$DATA1_REG_PHY_FIFO_WE_IN_DELAY_1                     = ($DDR_PHY_BASE_ADDR + 0x1BC)	
set	$DATA1_REG_PHY_DQ_OFFSET_0                     = ($DDR_PHY_BASE_ADDR + 0x1C0)	
set	$DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0                     = ($DDR_PHY_BASE_ADDR + 0x1C4)	
set	$DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_1                     = ($DDR_PHY_BASE_ADDR + 0x1C8)	
set	$DATA1_REG_PHY_WR_DATA_SLAVE_FORCE_0                     = ($DDR_PHY_BASE_ADDR + 0x1CC)	
set	$DATA1_REG_PHY_WR_DATA_SLAVE_DELAY_0                     = ($DDR_PHY_BASE_ADDR + 0x1D0)	
set	$DATA1_REG_PHY_WR_DATA_SLAVE_DELAY_1                     = ($DDR_PHY_BASE_ADDR + 0x1D4)	
set	$DATA1_REG_PHY_USE_RANK0_DELAYS_0                     = ($DDR_PHY_BASE_ADDR + 0x1D8)	
set	$DATA1_REG_PHY_DLL_LOCK_DIFF_0                     = ($DDR_PHY_BASE_ADDR + 0x1DC)	
set	$DATA1_PHY_REG_STATUS_DLL_LOCK_0                     = ($DDR_PHY_BASE_ADDR + 0x1E0)	
set	$DATA1_PHY_REG_STATUS_OF_IN_LOCK_STATE_0                     = ($DDR_PHY_BASE_ADDR + 0x1E4)	
set	$DATA1_PHY_REG_STATUS_OF_IN_DELAY_VALUE_0                     = ($DDR_PHY_BASE_ADDR + 0x1E8)	
set	$DATA1_PHY_REG_STATUS_OF_OUT_DELAY_VALUE_0                     = ($DDR_PHY_BASE_ADDR + 0x1EC)	
									
#FIFO									
set	$FIFO_WE_OUT0_IO_CONFIG_I_0                     = ($DDR_PHY_BASE_ADDR + 0x338)	
set	$FIFO_WE_OUT0_IO_CONFIG_SR_0                     = ($DDR_PHY_BASE_ADDR + 0x33C)	
set	$FIFO_WE_OUT1_IO_CONFIG_I_0                     = ($DDR_PHY_BASE_ADDR + 0x340)	
set	$FIFO_WE_OUT1_IO_CONFIG_SR_0                     = ($DDR_PHY_BASE_ADDR + 0x344)	
set	$FIFO_WE_IN2_IO_CONFIG_I_0                     = ($DDR_PHY_BASE_ADDR + 0x348)	
set	$FIFO_WE_IN2_IO_CONFIG_SR_0                     = ($DDR_PHY_BASE_ADDR + 0x34C)	
set	$FIFO_WE_IN3_IO_CONFIG_I_0                     = ($DDR_PHY_BASE_ADDR + 0x350)	
set	$FIFO_WE_IN3_IO_CONFIG_SR_0                     = ($DDR_PHY_BASE_ADDR + 0x354)	
									
#Leveling									
set	$DATA0_REG_PHY_WRLVL_NUM_OF_DQ0                     = ($DDR_PHY_BASE_ADDR + 0x35C)	
set	$DATA0_REG_PHY_GATELVL_NUM_OF_DQ0                     = ($DDR_PHY_BASE_ADDR + 0x360)	
set	$DATA1_REG_PHY_WRLVL_NUM_OF_DQ0                     = ($DDR_PHY_BASE_ADDR + 0x364)	
set	$DATA1_REG_PHY_GATELVL_NUM_OF_DQ0                     = ($DDR_PHY_BASE_ADDR + 0x368)	


#*******************************************************************
#Watchdog Timer registers
#*******************************************************************
set $WDT1_BASE_ADDR                                      = 0x44E35000  
set $WDT1_WSPR                                           = ($WDT1_BASE_ADDR + 0x48)

# Set JTAG speed to 30 kHz
monitor speed 1000

# Set GDBServer to little endian
monitor endian little

# Reset the chip to get to a known state.
monitor reset

#*******************************************************************
# CPU core initialization (to be done by user)
#*******************************************************************
# Set the processor mode

# http://www.lowlevel.eu/wiki/ARM#cpsr
# A (Imprecise Abort, deaktiviert solche) 
# I (IRQ disable, deaktiviert IRQs)  
# M (Mode, Nummer des aktuellen Prozessormodus, s. u.)  = 0x13 --> Abort
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
# info registers cpsr is not in sync with monitor reg cpsr
# therefore the GDB $cpsr register is being set manually
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
#set $cpsr = 0x800001B3
#set $cpsr &= ~0x20
#set $cpsr = ($cpsr & ~0x1F) | 0x13

# Result
monitor reg cpsr = 0x80000193

info registers cpsr
monitor reg cpsr

#**********************************************************************
#PLL Configuration functions
#**********************************************************************
define MPU_PLL_Config
	# MPU_PLL_Config(UWORD32 N,UWORD32 M,UWORD32 M2)
	# N Oscillator frequency-1
	p "MPU_PLL_Config"
	set $N = $arg0
	set $M = $arg1
	set $M2 = $arg2

	set $clkmode = *$CM_CLKMODE_DPLL_MPU
	set $clksel = *$CM_CLKSEL_DPLL_MPU
	set $div_m2 = *$CM_DIV_M2_DPLL_MPU

	p "****  Going to Bypass..."

	#put the DPLL in bypass mode
	# WR_MEM_32(CM_CLKMODE_DPLL_MPU,0x4);
	set *(unsigned int)$CM_CLKMODE_DPLL_MPU = 0x4
	#p "$CM_CLKMODE_DPLL_MPU"
	# Address
	#p/x $CM_CLKMODE_DPLL_MPU
	# Data
	#p/x *$CM_CLKMODE_DPLL_MPU

	while((*$CM_IDLEST_DPLL_MPU & 0x101) != 0x00000100)
		p "Waiting for DPLL bypass mode"
	end

	p "****  Bypassed, changing values..."

	#set multiply and divide values
	set $clksel = $clksel & (~0x7FFFF)
	set $clksel = $clksel | (($M <<0x8) | $N)
	# WR_MEM_32(CM_CLKSEL_DPLL_MPU,clksel);
	set *(unsigned int)$CM_CLKSEL_DPLL_MPU = $clksel
	set $div_m2 = $div_m2 & ~0x1F
	set $div_m2 = $div_m2 | $M2  
	# WR_MEM_32(CM_DIV_M2_DPLL_MPU,div_m2);
	set *(unsigned int)$CM_DIV_M2_DPLL_MPU = $div_m2
	
	p "****  Locking ARM PLL"
	
	#now lock the DPLL
	#enables lock mode
	set $clkmode |= 0x7
	#WR_MEM_32(CM_CLKMODE_DPLL_MPU,clkmode);
	set *(unsigned int)$CM_CLKMODE_DPLL_MPU = $clkmode
	#while(((RD_MEM_32(CM_IDLEST_DPLL_MPU) & 0x101) != 0x1)); 
	#wait for lock
	while((*$CM_IDLEST_DPLL_MPU & 0x101) != 0x1)
		p "Waiting for DPLL lock"
	end
end

define CORE_PLL_Config
	# CORE_PLL_Config(UWORD32 N,UWORD32 M,UWORD32 M4,UWORD32 M5,UWORD32 M6)
	# N Oscillator frequency-1
	p "CORE_PLL_Config"
	set $N = $arg0
	set $M = $arg1
	set $M4 = $arg2
	set $M5 = $arg3
	set $M6 = $arg4
	
	set $clkmode = *$CM_CLKMODE_DPLL_CORE
	set $clksel = *$CM_CLKSEL_DPLL_CORE
	set $div_m4 = *$CM_DIV_M4_DPLL_CORE 
	set $div_m5 = *$CM_DIV_M5_DPLL_CORE 
	set $div_m6 = *$CM_DIV_M6_DPLL_CORE 
	
	#put DPLL in bypass mode
	set $clkmode = ($clkmode & 0xfffffff8)|0x00000004
	#WR_MEM_32(CM_CLKMODE_DPLL_CORE,clkmode);
	set *(unsigned int)$CM_CLKMODE_DPLL_CORE = $clkmode

	while((*$CM_IDLEST_DPLL_CORE & 0x00000100 )!=0x00000100)
		p "Waiting for DPLL_CORE bypass mode"
	end

	p "****  Core Bypassed"
	
	#set multiply and divide values
	set $clksel = $clksel & (~0x7FFFF)
	set $clksel = $clksel | (($M <<0x8) | $N)
	#WR_MEM_32(CM_CLKSEL_DPLL_CORE,clksel);
	set *(unsigned int)$CM_CLKSEL_DPLL_CORE = $clksel
	#200MHz
	set $div_m4= $M4   
	#WR_MEM_32(CM_DIV_M4_DPLL_CORE,div_m4);
	set *(unsigned int)$CM_DIV_M4_DPLL_CORE = $div_m4
	#250MHz
	set $div_m5=  $M5  
	#WR_MEM_32(CM_DIV_M5_DPLL_CORE,div_m5);
	set *(unsigned int)$CM_DIV_M5_DPLL_CORE = $div_m5
	#500MHz
	set $div_m6=  $M6  
	#WR_MEM_32(CM_DIV_M6_DPLL_CORE,div_m6);
	set *(unsigned int)$CM_DIV_M6_DPLL_CORE = $div_m6

	p "****  Now locking Core..."

	#now lock the PLL
	set $clkmode =($clkmode&0xfffffff8)|0x00000007
	#WR_MEM_32(CM_CLKMODE_DPLL_CORE,clkmode);
	set *(unsigned int)$CM_CLKMODE_DPLL_CORE = $clkmode

	#while((RD_MEM_32(CM_IDLEST_DPLL_CORE) & 0x00000001 )!=0x00000001);
	while((*$CM_IDLEST_DPLL_CORE & 0x00000001 )!=0x00000001)
		p "Waiting for DPLL_CORE lock"
	end
	p "****  Core locked"
end

define DDR_PLL_Config
	# DDR_PLL_Config(UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2)
	# N Oscillator frequency-1
	p "DDR_PLL_Config"
	set $N = $arg0
	set $M = $arg1
	set $M2 = $arg2
	
	set $clkmode = *$CM_CLKMODE_DPLL_DDR
	set $clksel = *$CM_CLKSEL_DPLL_DDR
	set $div_m2 = *$CM_DIV_M2_DPLL_DDR 
	
	set $clkmode = ($clkmode & 0xfffffff8)|0x00000004
	#WR_MEM_32(CM_CLKMODE_DPLL_DDR,clkmode);
	set *(unsigned int)$CM_CLKMODE_DPLL_DDR = $clkmode

	while((*$CM_IDLEST_DPLL_DDR & 0x00000100 )!=0x00000100)
		p "Waiting for DPLL_DDR bypass mode"
	end

	p "****  DDR DPLL Bypassed"
	
	set $clksel = $clksel & (~0x7FFFF)
	set $clksel = $clksel | (($M <<0x8) | $N)
	#WR_MEM_32(CM_CLKSEL_DPLL_DDR,clksel);
	set *(unsigned int)$CM_CLKSEL_DPLL_DDR = $clksel
	set $div_m2 = *$CM_DIV_M2_DPLL_DDR
	set $div_m2 = ($div_m2&0xFFFFFFE0) | $M2
	#WR_MEM_32(CM_DIV_M2_DPLL_DDR,div_m2);
	set *(unsigned int)$CM_DIV_M2_DPLL_DDR = $div_m2
	set $clkmode =($clkmode&0xfffffff8)|0x00000007
	#WR_MEM_32(CM_CLKMODE_DPLL_DDR,clkmode);
	set *(unsigned int)$CM_CLKMODE_DPLL_DDR = $clkmode
	
	while((*$CM_IDLEST_DPLL_DDR & 0x00000001 )!=0x00000001)
		p "Waiting for DPLL_DDR locked"
	end

	p "****  DDR DPLL Locked"
end

define PER_PLL_Config
	# PER_PLL_Config(UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2)
	# N Oscillator frequency-1
	p "PER_PLL_Config"
	set $N = $arg0
	set $M = $arg1
	set $M2 = $arg2
	
	set $clkmode = *$CM_CLKMODE_DPLL_PER
	set $clksel = *$CM_CLKSEL_DPLL_PER
	set $div_m2 = *$CM_DIV_M2_DPLL_PER 
	
	set $clkmode =($clkmode&0xfffffff8)|0x00000004
	#WR_MEM_32(CM_CLKMODE_DPLL_PER,clkmode);
	set *(unsigned int)$CM_CLKMODE_DPLL_PER = $clkmode
	while((*$CM_IDLEST_DPLL_PER & 0x00000100 )!=0x00000100)
		p "Waiting for DPLL_PER bypass mode"
	end
	
	p "****  PER DPLL Bypassed"

	set $clksel = $clksel & (~0x7FFFF)
	set $clksel = $clksel | (($M <<0x8) | $N)
	#WR_MEM_32(CM_CLKSEL_DPLL_PER,clksel);
	set *(unsigned int)$CM_CLKSEL_DPLL_PER = $clksel
	set $div_m2 = 0xFFFFFF80 | $M2
	#WR_MEM_32(CM_DIV_M2_DPLL_PER,div_m2);
	set *(unsigned int)$CM_DIV_M2_DPLL_PER = $div_m2
	set $clkmode =($clkmode&0xfffffff8)|0x00000007
	#WR_MEM_32(CM_CLKMODE_DPLL_PER,clkmode);
	set *(unsigned int)$CM_CLKMODE_DPLL_PER = $clkmode
	
	while((*$CM_IDLEST_DPLL_PER & 0x00000001 )!=0x00000001)
		p "Waiting for DPLL_PER locked"
	end
	
	p "****  PER DPLL Locked"
end

define DISP_PLL_Config
	# DISP_PLL_Config(UWORD32 CLKIN,UWORD32 N,UWORD32 M,UWORD32 M2)
	# N Oscillator frequency-1
	p "DISP_PLL_Config"
	set $N = $arg0
	set $M = $arg1
	set $M2 = $arg2
	
	set $clkmode = *$CM_CLKMODE_DPLL_DISP
	set $clksel = *$CM_CLKSEL_DPLL_DISP
	set $div_m2 = *$CM_DIV_M2_DPLL_DISP 
	
	set $clkmode =($clkmode&0xfffffff8)|0x00000004
	#WR_MEM_32(CM_CLKMODE_DPLL_DISP,clkmode);
	set *(unsigned int)$CM_CLKMODE_DPLL_DISP = $clkmode
	while((*$CM_IDLEST_DPLL_DISP & 0x00000100 )!=0x00000100)
		p "Waiting for DPLL_DISP bypass mode"
	end
	
	set $clksel = $clksel & (~0x7FFFF)
	set $clksel = $clksel | (($M <<0x8) | $N)
	#WR_MEM_32(CM_CLKSEL_DPLL_DISP,clksel);
	set *(unsigned int)$CM_CLKSEL_DPLL_DISP = $clksel
	set $div_m2 = 0xFFFFFFE0 | $M2
	#WR_MEM_32(CM_DIV_M2_DPLL_DISP,div_m2);
	set *(unsigned int)$CM_DIV_M2_DPLL_DISP = $div_m2
	set $clkmode =($clkmode&0xfffffff8)|0x00000007
	#WR_MEM_32(CM_CLKMODE_DPLL_DISP,clkmode);
	set *(unsigned int)$CM_CLKMODE_DPLL_DISP = $clkmode
	
	while((*$CM_IDLEST_DPLL_DISP & 0x00000001 )!=0x00000001)
		p "Waiting for DPLL_DISP locked"
	end
	
	p "****  DISP PLL Config is DONE .........."
end

MPU_PLL_Config 24 300 1
CORE_PLL_Config 24 1000 10 8 4
DDR_PLL_Config 24 300 1
PER_PLL_Config 24 960 5
DISP_PLL_Config 24 48 1
p "****  AM335x ALL ADPLL Config for OPP == OPP100 is Done ........."

###############################################################################
###############################################################################
#                       DDR Configuration Section
###############################################################################
###############################################################################
set $CMD_PHY_CTRL_SLAVE_RATIO       = 0x80 
set $CMD_PHY_INVERT_CLKOUT		    = 0x00

set $DATA_PHY_RD_DQS_SLAVE_RATIO    = 0x38
set $DATA_PHY_FIFO_WE_SLAVE_RATIO   = 0x94 
set $DATA_PHY_WR_DQS_SLAVE_RATIO    = 0x44
set $DATA_PHY_WR_DATA_SLAVE_RATIO   = 0x7D

set $DDR_IOCTRL_VALUE               = 0x18B

#******************************************************************
#EMIF parameters
#******************************************************************

#RD_Latency = (CL + 2) - 1
set $ALLOPP_DDR3_READ_LATENCY      = 0x07         

#400MHz  
set $ALLOPP_DDR3_SDRAM_TIMING1   = 0x0AAAD4DB  
set $ALLOPP_DDR3_SDRAM_TIMING2   = 0x26437FDA    
set $ALLOPP_DDR3_SDRAM_TIMING3   = 0x501F83FF  

#termination = 1 (RZQ/4)  //old - 0x61C04AB2 
#dynamic ODT = 2 (RZQ/2)
#SDRAM drive = 0 (RZQ/6)
#CWL = 0 (CAS write latency = 5)
#CL=4 (CAS latency=6) #old - CL =  2 (CAS latency = 5)
#ROWSIZE = 5 (14 row bits)
#PAGESIZE = 2 (10 column bits)
set $ALLOPP_DDR3_SDRAM_CONFIG    = 0x61C05332

#400 * 7.8us = 0xC30
set $ALLOPP_DDR3_REF_CTRL        = 0x00000C30  

set $ALLOPP_DDR3_ZQ_CONFIG       = 0x50074BE4

define Enable_VTT_Regulator
	p "Enable_VTT_Regulator"
	#/*DDR_VTT_EN - GPIO0_18 PINMUX Setup*/     
    #WR_MEM_32(CONTROL_CONF_USB0_DRVVBUS, 0x27);
	set *(unsigned int)$CONTROL_CONF_USB0_DRVVBUS = 0x27

    #WR_MEM_32(CM_WKUP_GPIO0_CLKCTRL,0x40002);
	set *(unsigned int)$CM_WKUP_GPIO0_CLKCTRL = 0x40002
    #/* Poll if module is functional */
    #while(RD_MEM_32(CM_WKUP_GPIO0_CLKCTRL) & 0x30000 != 0x0);
	while((*$CM_WKUP_GPIO0_CLKCTRL & 0x30000) != 0x0)
		p "Waiting for module is functional 1"
	end
       
    #while( (RD_MEM_32(CM_WKUP_CLKSTCTRL) & 0x100) != 0x100);
	while((*$CM_WKUP_CLKSTCTRL & 0x100) != 0x100)
		p "Waiting for module is functional 2"
	end
	
    # reset the GPIO module
    #WR_MEM_32(GPIO0_SYSCONFIG,0x2);
	set *(unsigned int)$GPIO0_SYSCONFIG = 0x2
    #while(RD_MEM_32(GPIO0_SYSSTATUS)!= 0x1);
	while((*$GPIO0_SYSSTATUS) != 0x1)
		p "Waiting for module is functional 3"
	end
	
    # enable module
    #WR_MEM_32(GPIO0_CTRL,0x0); 
	set *(unsigned int)$GPIO0_CTRL = 0x0
    
    #/*enable output for GPIO0_18*/
     #WR_MEM_32((GPIO0_SETDATAOUT),(1<<18));
	 set *(unsigned int)$GPIO0_SETDATAOUT = (1<<18)
     #temp = RD_MEM_32(GPIO0_OE);
	 set $temp = *$GPIO0_OE
     #temp = temp & ~(1 << 18);
	 set $temp = $temp & ~(1 << 18)
     #WR_MEM_32(GPIO0_OE,temp);
	 set *(unsigned int)$GPIO0_OE = $temp
     #temp = temp | (1 << 18);
	 set $temp = $temp | (1 << 18)
     #WR_MEM_32(GPIO0_OE,temp);
	 set *(unsigned int)$GPIO0_OE = $temp
end

define EMIF_PRCM_CLK_ENABLE
	p "EMIF_PRCM_CLK_ENABLE"
	p "EMIF PRCM is in progress ......."
    #/* Enable EMIF4 Firewall clocks*/
    #WR_MEM_32(CM_PER_EMIF_FW_CLKCTRL,0x02);
	set *(unsigned int)$CM_PER_EMIF_FW_CLKCTRL = 0x02
    #/* Enable EMIF4 clocks*/
    #WR_MEM_32(CM_PER_EMIF_CLKCTRL,0x02);
	set *(unsigned int)$CM_PER_EMIF_CLKCTRL = 0x02
    #/* Poll if module is functional */
    #while(RD_MEM_32(CM_PER_EMIF_CLKCTRL)!= 0x02);
	while((*$CM_PER_EMIF_CLKCTRL) != 0x02)
		p "Waiting for CM_PER_EMIF_CLKCTRL != 0x02"
	end
    p "EMIF PRCM Done"
end

define VTP_Enable
	p "VTP_Enable"
	# Write 1 to enable VTP
    #WR_MEM_32(VTP_CTRL_REG ,(RD_MEM_32(VTP_CTRL_REG) | 0x00000040));
	set *(unsigned int)$VTP_CTRL_REG |= 0x00000040
      # Write 0 to CLRZ bit
    #WR_MEM_32(VTP_CTRL_REG ,(RD_MEM_32(VTP_CTRL_REG) & 0xFFFFFFFE));
	set *(unsigned int)$VTP_CTRL_REG &= 0xFFFFFFFE
      # Write 1 to CLRZ bit
    #WR_MEM_32(VTP_CTRL_REG ,(RD_MEM_32(VTP_CTRL_REG) | 0x00000001));
	set *(unsigned int)$VTP_CTRL_REG |= 0x00000001
     # Check for VTP ready bit
      p "Waiting for VTP Ready ......."
    #while((RD_MEM_32(VTP_CTRL_REG) & 0x00000020) != 0x00000020); 
	while((*$VTP_CTRL_REG & 0x00000020) != 0x00000020)
		p "Waiting for ((VTP_CTRL_REG) & 0x00000020) != 0x00000020)"
	end	  
    p "VTP is Ready!"
end

define PHY_Config_CMD
	p "PHY_Config_CMD"
	set $i = 0
    while ($i < 3)
       printf "DDR PHY CMD%d Register configuration is in progress .......\n",$i
       #WR_MEM_32(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 + (i*0x34),CMD_PHY_CTRL_SLAVE_RATIO);	   
	   set *(unsigned int)($CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 + $i*0x34) = $CMD_PHY_CTRL_SLAVE_RATIO
       #WR_MEM_32(CMD0_REG_PHY_INVERT_CLKOUT_0 + (i*0x34),CMD_PHY_INVERT_CLKOUT);
	   set *(unsigned int)($CMD0_REG_PHY_INVERT_CLKOUT_0 + $i*0x34) = $CMD_PHY_INVERT_CLKOUT
	   set $i += 1
	end
end

define PHY_Config_DATA
	p "PHY_Config_DATA"
	set $i = 0
    while ($i < 2)
		printf "DDR PHY DATA%d Register configuration is in progress ....... \n",$i
		#WR_MEM_32(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0     + (i*0xA4),DATA_PHY_RD_DQS_SLAVE_RATIO);
		set *(unsigned int)($DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0 + $i*0xA4) = $DATA_PHY_RD_DQS_SLAVE_RATIO
		#WR_MEM_32(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0     + (i*0xA4),DATA_PHY_WR_DQS_SLAVE_RATIO);
		set *(unsigned int)($DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0 + $i*0xA4) = $DATA_PHY_WR_DQS_SLAVE_RATIO
		#WR_MEM_32(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0    + (i*0xA4),DATA_PHY_FIFO_WE_SLAVE_RATIO);
		set *(unsigned int)($DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0 + $i*0xA4) = $DATA_PHY_FIFO_WE_SLAVE_RATIO
		#WR_MEM_32(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0    + (i*0xA4),DATA_PHY_WR_DATA_SLAVE_RATIO);
		set *(unsigned int)($DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0 + $i*0xA4) = $DATA_PHY_WR_DATA_SLAVE_RATIO
		set $i += 1
	end
end
	
define DDR3_EMIF_Config
	p "****  AM335x DDR3 EMIF and PHY configuration is in progress..."
	
	Enable_VTT_Regulator
	EMIF_PRCM_CLK_ENABLE
	
	p "DDR PHY Configuration in progress"
    
    VTP_Enable
	
	PHY_Config_CMD
    PHY_Config_DATA

    p "Setting IO control registers......."
	#WR_MEM_32(DDR_CMD0_IOCTRL,DDR_IOCTRL_VALUE);
	set *(unsigned int)$DDR_CMD0_IOCTRL = $DDR_IOCTRL_VALUE
    #WR_MEM_32(DDR_CMD1_IOCTRL,DDR_IOCTRL_VALUE);
	set *(unsigned int)$DDR_CMD1_IOCTRL = $DDR_IOCTRL_VALUE
    #WR_MEM_32(DDR_CMD2_IOCTRL,DDR_IOCTRL_VALUE);
	set *(unsigned int)$DDR_CMD2_IOCTRL = $DDR_IOCTRL_VALUE
    #WR_MEM_32(DDR_DATA0_IOCTRL,DDR_IOCTRL_VALUE);
	set *(unsigned int)$DDR_DATA0_IOCTRL = $DDR_IOCTRL_VALUE
    #WR_MEM_32(DDR_DATA1_IOCTRL,DDR_IOCTRL_VALUE);
	set *(unsigned int)$DDR_DATA1_IOCTRL = $DDR_IOCTRL_VALUE
	
	#IO to work for DDR3
    #WR_MEM_32(DDR_IO_CTRL, RD_MEM_32(DDR_IO_CTRL) & ~0x10000000 );
	set *(unsigned int)$DDR_IO_CTRL &= ~0x10000000

    #CKE controlled by EMIF/DDR_PHY
    #WR_MEM_32(DDR_CKE_CTRL, RD_MEM_32(DDR_CKE_CTRL) | 0x00000001);
	set *(unsigned int)$DDR_CKE_CTRL |= 0x00000001
	
    p "EMIF Timing register configuration is in progress ......."

    #WR_MEM_32(EMIF_DDR_PHY_CTRL_1_REG, ALLOPP_DDR3_READ_LATENCY);
	set *(unsigned int)$EMIF_DDR_PHY_CTRL_1_REG = $ALLOPP_DDR3_READ_LATENCY
    #WR_MEM_32(EMIF_DDR_PHY_CTRL_1_SHDW_REG, ALLOPP_DDR3_READ_LATENCY);
	set *(unsigned int)$EMIF_DDR_PHY_CTRL_1_SHDW_REG = $ALLOPP_DDR3_READ_LATENCY
    #WR_MEM_32(EMIF_DDR_PHY_CTRL_2_REG, ALLOPP_DDR3_READ_LATENCY);
	set *(unsigned int)$EMIF_DDR_PHY_CTRL_2_REG = $ALLOPP_DDR3_READ_LATENCY

    #WR_MEM_32(EMIF_SDRAM_TIM_1_REG,ALLOPP_DDR3_SDRAM_TIMING1);
	set *(unsigned int)$EMIF_SDRAM_TIM_1_REG = $ALLOPP_DDR3_SDRAM_TIMING1
    #WR_MEM_32(EMIF_SDRAM_TIM_1_SHDW_REG,ALLOPP_DDR3_SDRAM_TIMING1);
	set *(unsigned int)$EMIF_SDRAM_TIM_1_SHDW_REG = $ALLOPP_DDR3_SDRAM_TIMING1

    #WR_MEM_32(EMIF_SDRAM_TIM_2_REG,ALLOPP_DDR3_SDRAM_TIMING2);
	set *(unsigned int)$EMIF_SDRAM_TIM_2_REG = $ALLOPP_DDR3_SDRAM_TIMING2
    #WR_MEM_32(EMIF_SDRAM_TIM_2_SHDW_REG,ALLOPP_DDR3_SDRAM_TIMING2);
	set *(unsigned int)$EMIF_SDRAM_TIM_2_SHDW_REG = $ALLOPP_DDR3_SDRAM_TIMING2

    #WR_MEM_32(EMIF_SDRAM_TIM_3_REG,ALLOPP_DDR3_SDRAM_TIMING3);
	set *(unsigned int)$EMIF_SDRAM_TIM_3_REG = $ALLOPP_DDR3_SDRAM_TIMING3
    #WR_MEM_32(EMIF_SDRAM_TIM_3_SHDW_REG,ALLOPP_DDR3_SDRAM_TIMING3);
	set *(unsigned int)$EMIF_SDRAM_TIM_3_SHDW_REG = $ALLOPP_DDR3_SDRAM_TIMING3

    #WR_MEM_32(EMIF_SDRAM_REF_CTRL_REG,ALLOPP_DDR3_REF_CTRL);
	set *(unsigned int)$EMIF_SDRAM_REF_CTRL_REG = $ALLOPP_DDR3_REF_CTRL
    #WR_MEM_32(EMIF_SDRAM_REF_CTRL_SHDW_REG,ALLOPP_DDR3_REF_CTRL);
	set *(unsigned int)$EMIF_SDRAM_REF_CTRL_SHDW_REG = $ALLOPP_DDR3_REF_CTRL
    
    #WR_MEM_32(EMIF_ZQ_CONFIG_REG,ALLOPP_DDR3_ZQ_CONFIG);
	set *(unsigned int)$EMIF_ZQ_CONFIG_REG = $ALLOPP_DDR3_ZQ_CONFIG
    
    #WR_MEM_32(EMIF_SDRAM_CONFIG_REG, ALLOPP_DDR3_SDRAM_CONFIG);
	set *(unsigned int)$EMIF_SDRAM_CONFIG_REG = $ALLOPP_DDR3_SDRAM_CONFIG

    p "EMIF Timing register configuration is done ......."
	
	#if((RD_MEM_32(EMIF_STATUS_REG) & 0x4) == 0x4)
	if((*$EMIF_STATUS_REG & 0x4) == 0x4)
		p "PHY is READY!!"
    end

    p "DDR PHY Configuration done"
end

##########################################################################
#simple DDR test
##########################################################################

define DDR_DataTransferCheck
    #set $NO_LOOP_CNT       = 250
	set $NO_LOOP_CNT       = 8
	set $DDR_START_ADDR    = 0x80000000
	
	set $temp_reg_rd = 0
	set $temp_reg_wr = 0xA5A5A5A5
	set $error       = 0
    
	p "Try Accessing DDR memory....Write data 0xA5A5A5A5"
	set $i = 0
	while ($i < $NO_LOOP_CNT)
		# *((UWORD32 *)$DDR_START_ADDR + $i) = $temp_reg_wr
		set *(unsigned int)($DDR_START_ADDR + $i) = $temp_reg_wr
		printf "Data written at :: %x \n",(unsigned int)($DDR_START_ADDR + $i)
		set $i += 1
	end
	 
    set $i = 0
	while ($i < $NO_LOOP_CNT)
		set $temp_reg_rd =  *(unsigned int)($DDR_START_ADDR + $i)
        # GEL_TextOut("Data Read is :: %x \n",,,,,(unsigned int *)temp_reg_rd);
        if($temp_reg_rd != 0xA5A5A5A5)
           
            printf "Data check failed at :: %x value is :: %x\n",(unsigned int)($DDR_START_ADDR + $i),(unsigned int)$temp_reg_rd 

            set $error += 1    
        end   
             
		set $i += 1
	end
	
	printf "No of Failed locations  are :: %x \n",$error
	
	if($error != 0)
		p "Data Integrity check Failed"
	else
		p "Data Integrity check Passed"
	end
end

DDR3_EMIF_Config
DDR_DataTransferCheck

# Set JTAG speed to Auto
monitor speed Auto

# Set the Packet Size
set remote memory-write-packet-size 1025
set remote memory-write-packet-size fixed
set remote memory-read-packet-size 1025
set remote memory-read-packet-size fixed


#symbol-file barebox-am33xx-tben-lx-mx.img
#load barebox-am33xx-tben-lx-mx.img

#restore D:\Workspace_Linux\barebox-am33xx-tben-lx-mx-mlo.img binary 0x40000000
#restore D:\Workspace_Linux\barebox-am33xx-tben-lx-mx-mlo.img binary 0x80000000
restore D:\Workspace_Linux\barebox-am33xx-tben-lx-mx.img binary 0x80000000
#restore D:\Workspace_Linux\barebox.bin binary 0x80000000


#info registers pc
#monitor reg pc
monitor reg pc = 0x80000000
monitor go