/* * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /dts-v1/; #include "dra72x.dtsi" #include #include / { model = "TI AM5718 CUSTOM BOARD"; compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7"; memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x20000000>; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; dsp1_cma_pool: dsp1_cma@99000000 { compatible = "shared-dma-pool"; reg = <0x0 0x99000000 0x0 0x4000000>; reusable; status = "okay"; }; cmem_block_mem_0: cmem_block_mem@90000000 { reg = <0x0 0x90000000 0x0 0x05800000>; no-map; status = "okay"; }; }; cmem { compatible = "ti,cmem"; #address-cells = <1>; #size-cells = <0>; #pool-size-cells = <2>; status = "okay"; cmem_block_0: cmem_block@0 { reg = <0>; memory-region = <&cmem_block_mem_0>; cmem-buf-pools = <1 0x0 0x05800000>; }; }; }; &dra7_pmx_core { i2c1_pins_default: i2c1_pins_default { pinctrl-single,pins = < 0x404 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* I2C1 - i2c1_scl on C20 - I2C_GPC_PMIC */ 0x400 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* I2C1 - i2c1_sda on C21 - I2C_GPC_PMIC */ >; }; i2c2_pins_default: i2c2_pins_default { pinctrl-single,pins = < 0x40C (PIN_INPUT | PULL_DIS | MUX_MODE0) /* I2C2 - i2c2_scl on F17 - I2C2_AVS_PMIC */ 0x408 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* I2C2 - i2c2_sda on C25 - I2C2_AVS_PMIC */ >; }; uart1_pins_default: uart1_pins_default { pinctrl-single,pins = < 0x3E0 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* UART1 - uart1_rxd on B27 - UART1 (UART1_RXD) */ 0x3E4 (PIN_OUTPUT | PULL_DIS | MUX_MODE0) /* UART1 - uart1_txd on C26 - UART1 (UART1_TXD) */ >; }; uart3_pins_default: uart3_pins_default { pinctrl-single,pins = < 0x3F8 (PIN_INPUT | PULL_DIS | MUX_MODE2) /* UART3 - uart3_rxd on D27 - UART3 (UART2_CTSN) */ 0x3FC (PIN_OUTPUT | PULL_DIS | MUX_MODE1) /* UART3 - uart3_txd on C28 - UART3 (UART2_RTSN) */ >; }; pruss1_uart_pins_default: pruss1_uart_pins_default { pinctrl-single,pins = < 0x168 (PIN_INPUT | PULL_DIS | MUX_MODE11) /* PRUSS1_UART - pr1_uart0_rxd on F2 - PRU_UART3 */ 0x16C (PIN_OUTPUT | PULL_DIS | MUX_MODE11) /* PRUSS1_UART - pr1_uart0_txd on F3 - PRU_UART3 */ >; }; spi_pins_default: spi_pins_default { pinctrl-single,pins = < 0x394 (PIN_OUTPUT | PULL_DIS | MUX_MODE1) /* SPI4 - spi4_sclk on AC8 - TECU */ 0x39C (PIN_OUTPUT | PULL_DIS | MUX_MODE1) /* SPI4 - spi4_d0 on AB8 - TECU */ 0x398 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* SPI4 - spi4_d1 on AD6 - TECU */ 0x3A0 (PIN_OUTPUT | PULL_DIS | MUX_MODE1) /* SPI4 - spi4_cs0 on AB5 - TECU */ 0x3A4 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* SPI1 - spi1_sclk on A25 - LO_SPI_ADC */ 0x3B0 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* SPI1 - spi1_cs0 on A24 - LO_SPI_ADC */ 0x3AC (PIN_INPUT | PULL_DIS | MUX_MODE0) /* SPI1 - spi1_d0 on B25 - LO_SPI_ADC */ >; }; mcspi3_pins: mcspi3_pins { pinctrl-single,pins = < 0x380 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* SPI3 - spi3_sclk on AC4 - DIVIO AVM */ 0x388 (PIN_OUTPUT | PULL_DIS | MUX_MODE1) /* SPI3 - spi3_d0 on AC6 - DIVIO AVM */ 0x384 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* SPI3 - spi3_d1 on AC7 - DIVIO AVM */ 0x38C (PIN_INPUT | PULL_DIS | MUX_MODE1) /* SPI3 - spi3_cs0 on AC9 - DIVIO AVM */ >; }; gpio_pins_default: gpio_pins_default { pinctrl-single,pins = < 0x158 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO3 - gpio3_29 on G2 - GPIO3 */ 0x164 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_0 on G6 - GPIO4 */ 0x170 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_3 on D1 - GPIO4 */ 0x174 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_4 on E2 - GPIO4 */ 0x178 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_5 on D2 - GPIO4 */ 0x17C (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_6 on F4 - GPIO4 */ 0x184 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_8 on E4 - GPIO4 */ 0x190 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_11 on D3 - GPIO4 */ 0x198 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_13 on D5 - GPIO4 */ 0x19C (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_14 on C2 - GPIO4 */ 0x1A0 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_15 on C3 - GPIO4 */ 0x1AC (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_25 on D6 - GPIO4 */ 0x1B0 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_26 on C5 - GPIO4 */ 0x1B4 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* GPIO4 - gpio4_27 on A3 - GPIO4 */ >; }; gpio_pins_virtual: gpio_pins_virtual { pinctrl-single,pins = < 0x154 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE11 | MUX_MODE14) /* GPIO3 - gpio3_28 on E1 - GPIO3 */ 0x15C (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE11 | MUX_MODE14) /* GPIO3 - gpio3_30 on H7 - GPIO3 */ 0x160 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE9 | MUX_MODE14) /* GPIO3 - gpio3_31 on G1 - GPIO3 */ 0x188 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE9 | MUX_MODE14) /* GPIO4 - gpio4_9 on F5 - GPIO4 */ 0x194 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE9 | MUX_MODE14) /* GPIO4 - gpio4_12 on F6 - GPIO4 */ >; }; int_pins_default: int_pins_default { pinctrl-single,pins = < 0x424 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* INTC - sys_nirq1 on AC16 - INT */ 0x418 (PIN_INPUT | PULL_DIS | MUX_MODE14) /* INTC - sys_nirq2 on AD17 - INT */ >; }; mdio_pins_default: mdio_pins_default { pinctrl-single,pins = < 0x3B8 (PIN_OUTPUT | PULL_DIS | MUX_MODE5) /* MDIO - mdio_mclk on B21 - MDIO_PHY */ 0x3BC (PIN_INPUT | PULL_DIS | MUX_MODE5) /* MDIO - mdio_d on B20 - MDIO_PHY */ >; }; gpmc_pins_default: gpmc_pins_default { pinctrl-single,pins = < 0x1C (PIN_INPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_ad7 on L2 - NAND */ 0x18 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_ad6 on L3 - NAND */ 0x14 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_ad5 on L4 - NAND */ 0x10 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_ad4 on L6 - NAND */ 0xC (PIN_INPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_ad3 on M1 - NAND */ 0x8 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_ad2 on L5 - NAND */ 0x4 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_ad1 on M2 - NAND */ 0x0 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_ad0 on M6 - NAND */ 0xD8 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_wait0 on N2 - NAND */ 0xC0 (PIN_INPUT | PULL_DIS | MUX_MODE3) /* GPMC - gpmc_wait1 on P7 - NAND */ 0xB4 (PIN_OUTPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_cs0 on T1 - NAND */ 0xB0 (PIN_OUTPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_cs1 on H6 - NAND */ 0xC4 (PIN_OUTPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_advn_ale on N1 - NAND */ 0xC8 (PIN_OUTPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_oen_ren on M5 - NAND */ 0xCC (PIN_OUTPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_wen on M3 - NAND */ 0xD0 (PIN_OUTPUT | PULL_DIS | MUX_MODE0) /* GPMC - gpmc_ben0 on N6 - NAND */ >; }; gpmc_pins_virtual: gpmc_pins_virtual { pinctrl-single,pins = < 0x1C (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0) /* GPMC - gpmc_ad7 on L2 - NAND */ 0x18 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0) /* GPMC - gpmc_ad6 on L3 - NAND */ 0x14 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0) /* GPMC - gpmc_ad5 on L4 - NAND */ 0x10 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0) /* GPMC - gpmc_ad4 on L6 - NAND */ 0xC (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0) /* GPMC - gpmc_ad3 on M1 - NAND */ 0x8 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0) /* GPMC - gpmc_ad2 on L5 - NAND */ 0x4 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0) /* GPMC - gpmc_ad1 on M2 - NAND */ 0x0 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0) /* GPMC - gpmc_ad0 on M6 - NAND */ 0xD8 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* GPMC - gpmc_wait0 on N2 - NAND */ 0xC0 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE3) /* GPMC - gpmc_wait1 on P7 - NAND */ 0xB4 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* GPMC - gpmc_cs0 on T1 - NAND */ 0xB0 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* GPMC - gpmc_cs1 on H6 - NAND */ 0xC4 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* GPMC - gpmc_advn_ale on N1 - NAND */ 0xC8 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* GPMC - gpmc_oen_ren on M5 - NAND */ 0xCC (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* GPMC - gpmc_wen on M3 - NAND */ 0xD0 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* GPMC - gpmc_ben0 on N6 - NAND */ >; }; qspi1_pins_default: qspi1_pins_default { pinctrl-single,pins = < 0x88 (PIN_OUTPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_sclk on R2 - NOR */ 0x74 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_rtclk on R3 - NOR */ 0xB8 (PIN_OUTPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_cs0 on P2 - NOR */ 0xBC (PIN_OUTPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_cs1 on P1 - NOR */ 0x80 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_d0 on U1 - NOR */ 0x84 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_d1 on P3 - NOR */ 0x7C (PIN_INPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_d2 on U2 - NOR */ 0x78 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_d3 on T2 - NOR */ >; }; qspi1_pins_manual: qspi1_pins_manual { pinctrl-single,pins = < 0x88 (PIN_OUTPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_sclk on R2 - NOR */ 0x74 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_rtclk on R3 - NOR */ 0xB8 (PIN_OUTPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_cs0 on P2 - NOR */ 0xBC (PIN_OUTPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_cs1 on P1 - NOR */ 0x80 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_d0 on U1 - NOR */ 0x84 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_d1 on P3 - NOR */ 0x7C (PIN_INPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_d2 on U2 - NOR */ 0x78 (PIN_INPUT | PULL_DIS | MUX_MODE1) /* QSPI1 - qspi1_d3 on T2 - NOR */ >; }; qspi1_pins_virtual1: qspi1_pins_virtual1 { pinctrl-single,pins = < 0x88 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE14 | MUX_MODE1) /* QSPI1 - qspi1_sclk on R2 - NOR */ 0x74 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE14 | MUX_MODE1) /* QSPI1 - qspi1_rtclk on R3 - NOR */ 0xB8 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE14 | MUX_MODE1) /* QSPI1 - qspi1_cs0 on P2 - NOR */ 0xBC (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* QSPI1 - qspi1_cs1 on P1 - NOR */ 0x7C (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE14 | MUX_MODE1) /* QSPI1 - qspi1_d2 on U2 - NOR */ 0x78 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE14 | MUX_MODE1) /* QSPI1 - qspi1_d3 on T2 - NOR */ >; }; qspi1_pins_virtual2: qspi1_pins_virtual2 { pinctrl-single,pins = < 0x88 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* QSPI1 - qspi1_sclk on R2 - NOR */ 0x74 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* QSPI1 - qspi1_rtclk on R3 - NOR */ 0xB8 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* QSPI1 - qspi1_cs0 on P2 - NOR */ 0xBC (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE12 | MUX_MODE1) /* QSPI1 - qspi1_cs1 on P1 - NOR */ 0x7C (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* QSPI1 - qspi1_d2 on U2 - NOR */ 0x78 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* QSPI1 - qspi1_d3 on T2 - NOR */ >; }; debug_pins_trace: debug_pins_trace { pinctrl-single,pins = < 0x430 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* DEBUGSS - tms on F18 - TRACE PORT */ 0x434 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* DEBUGSS - tdi on D23 - TRACE PORT */ 0x438 (PIN_OUTPUT | PULL_DIS | MUX_MODE0) /* DEBUGSS - tdo on F19 - TRACE PORT */ 0x43C (PIN_INPUT | PULL_DIS | MUX_MODE0) /* DEBUGSS - tclk on E20 - TRACE PORT */ 0x440 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* DEBUGSS - trstn on D20 - TRACE PORT */ 0x444 (PIN_OUTPUT | PULL_DIS | MUX_MODE0) /* DEBUGSS - rtck on E18 - TRACE PORT */ 0x448 (PIN_INPUT | PULL_DIS | MUX_MODE0) /* DEBUGSS - emu0 on G21 - TRACE PORT */ 0x44C (PIN_INPUT | PULL_DIS | MUX_MODE0) /* DEBUGSS - emu1 on D24 - TRACE PORT */ 0x1E4 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu2 on F10 - TRACE PORT */ 0x204 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu3 on D7 - TRACE PORT */ 0x224 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu4 on A7 - TRACE PORT */ 0x1E8 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu5 on G11 - TRACE PORT */ 0x1EC (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu6 on E9 - TRACE PORT */ 0x1F0 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu7 on F9 - TRACE PORT */ 0x1F4 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu8 on F8 - TRACE PORT */ 0x1F8 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu9 on E7 - TRACE PORT */ 0x208 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu10 on D8 - TRACE PORT */ 0x20C (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu11 on A5 - TRACE PORT */ 0x210 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu12 on C6 - TRACE PORT */ 0x214 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu13 on C8 - TRACE PORT */ 0x218 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu14 on C7 - TRACE PORT */ 0x228 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu15 on A8 - TRACE PORT */ 0x22C (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu16 on C9 - TRACE PORT */ 0x230 (PIN_OUTPUT | PULL_DIS | MUX_MODE2) /* DEBUGSS - emu17 on A9 - TRACE PORT */ >; }; }; &elm { status = "okay"; }; &mac { status = "okay"; dual_emac; }; &cpsw_emac0 { phy-mode = "rmii"; dual_emac_res_vlan = <1>; fixed-link { speed = <10>; full-duplex; }; }; &cpsw_emac1 { phy-mode = "rmii"; dual_emac_res_vlan = <2>; fixed-link { speed = <100>; full-duplex; }; }; &phy_sel { rmii-clock-ext; }; &gpmc { status = "okay"; ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ pinctrl-names = "default"; pinctrl-0 = <&gpmc_pins_default>; nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* device IO registers */ ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <100>; gpmc,cs-wr-off-ns = <100>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <100>; gpmc,adv-wr-off-ns = <100>; gpmc,we-on-ns = <10>; gpmc,we-off-ns = <60>; gpmc,oe-on-ns = <4>; gpmc,oe-off-ns = <60>; gpmc,access-ns = <50>; gpmc,wr-access-ns = <80>; gpmc,rd-cycle-ns = <100>; gpmc,wr-cycle-ns = <100>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wait-monitoring-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <2>; partition@0 { label = "mtd_nand"; reg = <0x00000000 0x1 0x00000000>; }; }; }; &qspi { status = "okay"; spi-max-frequency = <48000000>; n25q512a@0 { compatible = "micron,n25q512a"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-cpol; spi-cpha; #address-cells = <1>; #size-cells = <1>; /* MTD partition table. * The ROM checks the first four physical blocks * for a valid file to boot and the flash here is * 64KiB block size. */ /* ------------------------------------------------- */ /* Reserve 1MB for MLO + U-Boot + u-Boot Environment */ /* ------------------------------------------------- */ partition@0 { label = "mtd_part1_mlo"; reg = <0x00000000 0x00020000>; }; partition@1 { label = "mtd_part1_uboot"; reg = <0x00020000 0x000D0000>; }; partition@2 { label = "mtd_part1_env"; reg = <0x000F0000 0x00010000>; }; /* ------------------------------------------------ */ /* Reserve 11MB for PART1 zImage + DTB */ /* ------------------------------------------------ */ partition@3 { label = "mtd_part1_zimage"; reg = <0x00100000 0x00AC0000>; }; partition@4 { label = "mtd_part1_dtb"; reg = <0x00BC0000 0x00040000>; }; /* ------------------------------------------------ */ /* Reserve 8MB for the custom app */ /* ------------------------------------------------ */ partition@5 { label = "mtd_custom_app"; reg = <0x00C00000 0x00800000>; }; /* ------------------------------------------------ */ /* Reserve 24MB for PART2 zImage + DTB */ /* ------------------------------------------------ */ partition@6 { label = "mtd_part2_zimage"; reg = <0x01400000 0x017C0000>; }; partition@7 { label = "mtd_part2_dtb"; reg = <0x02BC0000 0x00040000>; }; /* ------------------------------------------------ */ /* Reserve 20MB for OTHERS */ /* ------------------------------------------------ */ partition@8 { label = "mtd_loads"; reg = <0x02C00000 0x01400000>; }; }; }; &uart1 { status = "okay"; }; &uart3 { status = "okay"; }; &usb2 { dr_mode = "host"; }; &mcspi3 { status = "okay"; ti,spi-num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&mcspi3_pins>; divio: divio@0 { compatible = "customspidriver"; spi-max-frequency = <48000000>; reg = <0>; status = "okay"; }; }; &mailbox5 { status = "okay"; mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { status = "okay"; }; mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { status = "okay"; }; }; &mmu0_dsp1 { status = "okay"; }; &mmu1_dsp1 { status = "okay"; }; &mmu_ipu1 { status = "okay"; }; &dsp1 { status = "okay"; memory-region = <&dsp1_cma_pool>; mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; timers = <&timer5>; };