// SPDX-License-Identifier: GPL-2.0
/*
 * Reference is k3-j721s2-common-proc-board-u-boot.dtss
 */

/ {
	chosen {
		stdout-path = "serial2:115200n8";
		tick-timer = &timer1;
	};

	aliases {
		serial0 = &wkup_uart0;
		serial1 = &mcu_uart0;
		serial2 = &main_uart8;
		i2c0 = &wkup_i2c0;
		i2c1 = &mcu_i2c0;
		i2c2 = &mcu_i2c1;
		i2c3 = &main_i2c0;
		ethernet0 = &main_cpsw_port1;
		spi0 = &ospi0;
		mmc0 = &main_sdhci0;
	};
};

&cbass_main {
	u-boot,dm-spl;
};

&main_navss {
	u-boot,dm-spl;
};

&cbass_mcu_wakeup {
	u-boot,dm-spl;

	timer1: timer@40400000 {
		compatible = "ti,omap5430-timer";
		reg = <0x0 0x40400000 0x0 0x80>;
		ti,timer-alwon;
		clock-frequency = <25000000>;
		u-boot,dm-spl;
	};

	chipid@43000014 {
		u-boot,dm-spl;
	};
};

&mcu_navss {
	u-boot,dm-spl;
};

&mcu_ringacc {
	reg =   <0x0 0x2b800000 0x0 0x400000>,
		<0x0 0x2b000000 0x0 0x400000>,
		<0x0 0x28590000 0x0 0x100>,
		<0x0 0x2a500000 0x0 0x40000>,
		<0x0 0x28440000 0x0 0x40000>;
	reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
	u-boot,dm-spl;
};

&mcu_udmap {
	reg =   <0x0 0x285c0000 0x0 0x100>,
		<0x0 0x284c0000 0x0 0x4000>,
		<0x0 0x2a800000 0x0 0x40000>,
		<0x0 0x284a0000 0x0 0x4000>,
		<0x0 0x2aa00000 0x0 0x40000>,
		<0x0 0x28400000 0x0 0x2000>;
	reg-names = "gcfg", "rchan", "rchanrt", "tchan",
		    "tchanrt", "rflow";
	u-boot,dm-spl;
};

&secure_proxy_main {
	u-boot,dm-spl;
};

&sms {
	u-boot,dm-spl;
	k3_sysreset: sysreset-controller {
		compatible = "ti,sci-sysreset";
		u-boot,dm-spl;
	};
};

&main_pmx0 {
	u-boot,dm-spl;
};

// &main_mmc0_pins_default {
// 	u-boot,dm-spl;
// };

// &main_usbss0_pins_default {
// 	u-boot,dm-spl;
// };

&main_uart8 {
	u-boot,dm-spl;
};

&wkup_pmx0 {
	u-boot,dm-spl;
};

&k3_pds {
	u-boot,dm-spl;
};

&k3_clks {
	u-boot,dm-spl;
};

&k3_reset {
	u-boot,dm-spl;
};


&mcu_uart0 {
	u-boot,dm-spl;
};

&wkup_uart0 {
	u-boot,dm-spl;
};

&fss {
	u-boot,dm-spl;
};

&mcu_cpsw {
	reg = <0x0 0x46000000 0x0 0x200000>,
	      <0x0 0x40f00200 0x0 0x8>;
	reg-names = "cpsw_nuss", "mac_efuse";
	/delete-property/ ranges;

	cpsw-phy-sel@40f04040 {
        	compatible = "ti,am654-cpsw-phy-sel";
		reg= <0x0 0x40f04040 0x0 0x4>;
		reg-names = "gmii-sel";
        };
};

&main_cpsw {
	/delete-property/ ranges;

	cpsw-phy-sel@104034 {
        	compatible = "ti,am654-cpsw-phy-sel";
		reg= <0x0 0x104034 0x0 0x4>;
		reg-names = "gmii-sel";
        };
};

&mymcu_ospi1_pins_default {
	u-boot,dm-spl;
};

&main_r5fss0 {
	ti,cluster-mode = <0>;
};

&main_r5fss1 {
	ti,cluster-mode = <0>;
};

&wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>, <&wiz0_pll0_refclk>;
	assigned-clock-parents = <&k3_clks 365 40>, <&k3_clks 365 75>;
};

&serdes_ln_ctrl {
	u-boot,mux-autoprobe;
};

&usb_serdes_mux {
	u-boot,mux-autoprobe;
};

&ospi0 {
	u-boot,dm-spl;

	flash@0 {
		cdns,phy-mode;
		u-boot,dm-spl;

		partition@3fc0000 {
			label = "ospi.phypattern";
			reg = <0x3fc0000 0x40000>;
			u-boot,dm-spl;
		};
	};
};

&main_sdhci0 {
	u-boot,dm-spl;
};