(virtual-env-edgeai) admin@VM2502:~/jay/python-virtual-env/edgeai-tidl-tools/examples/osrt_python/tfl$ python3 ./tflrt_delegate.py -m cl-0000_tflitert_imagenet1k_mlperf_mobilenet_v1_1.0_224_tflite -c Running 1 Models - ['cl-0000_tflitert_imagenet1k_mlperf_mobilenet_v1_1.0_224_tflite'] Running_Model : cl-0000_tflitert_imagenet1k_mlperf_mobilenet_v1_1.0_224_tflite tidl_tools_path = /home/admin/jay/python-virtual-env/edgeai-tidl-tools/tools/AM62A/tidl_tools artifacts_folder = ../../../model-artifacts//cl-0000_tflitert_imagenet1k_mlperf_mobilenet_v1_1.0_224_tflite/artifacts tidl_tensor_bits = 8 debug_level = 2 num_tidl_subgraphs = 16 num_tidl_subgraph_max_node = 0 enable_rt_multi_subgraph_support = 0 tidl_denylist = tidl_denylist_layer_name = tidl_denylist_layer_type = tidl_allowlist_layer_name = model_type = tidl_calibration_accuracy_level = 7 tidl_calibration_options:num_frames_calibration = 2 tidl_calibration_options:bias_calibration_iterations = 5 mixed_precision_factor = -1.000000 model_group_id = 0 power_of_2_quantization = 2 ONNX QDQ Enabled = 0 enable_high_resolution_optimization = 0 pre_batchnorm_fold = 1 add_data_convert_ops = 3 output_feature_16bit_names_list = m_params_16bit_names_list = m_single_core_layers_names_list = Inference mode = 0 Number of cores = 1 reserved_compile_constraints_flag = 1601 partial_init_during_compile = 0 packetize_mode = 0 ti_internal_reserved_1 = ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 10_01_04_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 10_01_00_01 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 65 Tflite layer type --- 53 layer output name--- MobilenetV1/MobilenetV1/Conv2d_0/Relu6/Mul/Bias/InCast -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 5 Tflite layer type --- 0 layer output name--- MobilenetV1/MobilenetV1/Conv2d_0/Relu6/Mul/Bias -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 5 Tflite layer type --- 18 layer output name--- MobilenetV1/MobilenetV1/Conv2d_0/Relu6/Mul -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_0/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_1_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_1_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_2_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_2_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_3_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_3_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_4_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_4_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_5_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_5_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_6_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_6_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_7_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_7_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_8_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_8_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_9_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_9_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_10_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_10_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_11_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_11_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_12_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_12_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 4 layer output name--- MobilenetV1/MobilenetV1/Conv2d_13_depthwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/MobilenetV1/Conv2d_13_pointwise/Relu6 -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 2 Tflite layer type --- 1 layer output name--- MobilenetV1/Logits/AvgPool_1a/AvgPool -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 1 Tflite layer type --- 3 layer output name--- MobilenetV1/Logits/Conv2d_1c_1x1/BiasAdd -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 34 Tflite layer type --- 43 layer output name--- MobilenetV1/Logits/SpatialSqueeze -- [tidl_tfLiteRtImport_core.cpp, 3096] [TIDL Import] [PARSER] SUPPORTED: Supported TIDL layer type --- 7 Tflite layer type --- 25 layer output name--- MobilenetV1/Predictions/Reshape_1 -- [tidl_tfLiteRtImport_core.cpp, 3096] Total Nodes = 34 ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 34 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= In TIDL_tfliteRtImportInit subgraph_id=86 Layer 0, subgraph id 86, name=MobilenetV1/Predictions/Reshape_1 Layer 1, subgraph id 86, name=input In TIDL_tfliteRtImportNode, TIDL Layer type - 65, Tflite builtin code type - 53 In TIDL_tfliteRtImportNode, TIDL Layer type - 5, Tflite builtin code type - 0 In TIDL_tfliteRtImportNode, TIDL Layer type - 5, Tflite builtin code type - 18 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 4 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 2, Tflite builtin code type - 1 In TIDL_tfliteRtImportNode, TIDL Layer type - 1, Tflite builtin code type - 3 In TIDL_tfliteRtImportNode, TIDL Layer type - 34, Tflite builtin code type - 43 In TIDL_tfliteRtImportNode, TIDL Layer type - 7, Tflite builtin code type - 25 ==================== [Optimization for subgraph_86 started] ==================== In TIDL_runtimesOptimizeNet: LayerIndex = 36, dataIndex = 35 [TIDL Import] [PARSER] WARNING: Requested output data convert layer is not added to the network, It is currently not optimal ----------------------------- Optimization Summary ----------------------------- -------------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | -------------------------------------------------------------------------------- | TIDL_SoftMaxLayer | 1 | 1 | | TIDL_SqueezeLayer | 1 | 0 | | TIDL_ConvolutionLayer | 28 | 28 | | TIDL_EltWiseLayer | 2 | 0 | | TIDL_CastLayer | 1 | 0 | | TIDL_PoolingLayer | 1 | 1 | -------------------------------------------------------------------------------- =================== [Optimization for subgraph_86 completed] =================== In TIDL_runtimesPostProcessNet ************ in TIDL_subgraphRtCreate ************ The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INIT:Enabled 0.33s: VX_ZONE_ERROR:Enabled 0.42s: VX_ZONE_WARNING:Enabled 0.6774s: VX_ZONE_INIT:[tivxInit:190] Initialization Done !!! -------------------------------------------- TIDL Memory size requiement (record wise): MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 2 , DDR Cacheable , Scratch , 128, 16.00 , 0x00000000 3 , DDR Cacheable , Scratch , 128, 4.00 , 0x00000000 4 , DDR Cacheable , Scratch , 128, 56.00 , 0x00000000 5 , DDR Cacheable , Persistent , 128, 361.32 , 0x00000000 6 , DDR Cacheable , Scratch , 128, 7244.41 , 0x00000000 7 , DDR Cacheable , Scratch , 128, 0.12 , 0x00000000 8 , DDR Cacheable , Scratch , 128, 4873.25 , 0x00000000 9 , DDR Cacheable , Scratch , 128, 6500.50 , 0x00000000 10 , DDR Cacheable , Persistent , 128, 567.80 , 0x00000000 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 12 , DDR Cacheable , Persistent , 128, 0.12 , 0x00000000 13 , DDR Cacheable , Persistent , 128, 22768.88, 0x00000000 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 15 , DDR Cacheable , Persistent , 128, 0.12 , 0x00000000 -------------------------------------------- Total memory size requirement (space wise): Mem Space , Size(KBytes) DDR Cacheable, 42924.71 -------------------------------------------- NOTE: Memory requirement in host emulation can be different from the same on EVM To get the actual TIDL memory requirement make sure to run on EVM with debugTraceLevel = 2 -------------------------------------------- TIDL init call from ivision API -------------------------------------------- TIDL Memory size requiement (record wise): MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x89c13000 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x8c76a000 2 , DDR Cacheable , Scratch , 128, 16.00 , 0x89c0f000 3 , DDR Cacheable , Scratch , 128, 4.00 , 0x8be84000 4 , DDR Cacheable , Scratch , 128, 56.00 , 0x889cb000 5 , DDR Cacheable , Persistent , 128, 361.32 , 0x88970000 6 , DDR Cacheable , Scratch , 128, 7244.41 , 0x872f5000 7 , DDR Cacheable , Scratch , 128, 0.12 , 0x8be83000 8 , DDR Cacheable , Scratch , 128, 4873.25 , 0x86b99000 9 , DDR Cacheable , Scratch , 128, 6500.50 , 0x820a6000 10 , DDR Cacheable , Persistent , 128, 567.80 , 0x888e2000 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x88861000 12 , DDR Cacheable , Persistent , 128, 0.12 , 0x89c0e000 13 , DDR Cacheable , Persistent , 128, 22768.88, 0x2a186000 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x89c0d000 15 , DDR Cacheable , Persistent , 128, 0.12 , 0x89c0c000 -------------------------------------------- Total memory size requirement (space wise): Mem Space , Size(KBytes) DDR Cacheable, 42924.71 -------------------------------------------- NOTE: Memory requirement in host emulation can be different from the same on EVM To get the actual TIDL memory requirement make sure to run on EVM with debugTraceLevel = 2 -------------------------------------------- Alg Init for Layer # - 1 Alg Init for Layer # - 2 Alg Init for Layer # - 3 Alg Init for Layer # - 4 Alg Init for Layer # - 5 Alg Init for Layer # - 6 Alg Init for Layer # - 7 Alg Init for Layer # - 8 Alg Init for Layer # - 9 Alg Init for Layer # - 10 Alg Init for Layer # - 11 Alg Init for Layer # - 12 Alg Init for Layer # - 13 Alg Init for Layer # - 14 Alg Init for Layer # - 15 Alg Init for Layer # - 16 Alg Init for Layer # - 17 Alg Init for Layer # - 18 Alg Init for Layer # - 19 Alg Init for Layer # - 20 Alg Init for Layer # - 21 Alg Init for Layer # - 22 Alg Init for Layer # - 23 Alg Init for Layer # - 24 Alg Init for Layer # - 25 Alg Init for Layer # - 26 Alg Init for Layer # - 27 Alg Init for Layer # - 28 Alg Init for Layer # - 29 Alg Init for Layer # - 30 Alg Init for Layer # - 31 Alg Init for Layer # - 32 Alg Init for Layer # - 33 Alg Init for Layer # - 34 PREEMPTION: Adding a new priority object for targetPriority = 0, handle = 0x7f0889c13000 PREEMPTION: Now total number of priority objects = 1 at priorityId = 0, with new memRec of base = 0x7f0889c0e000 and size = 128 PREEMPTION: Requesting context memory addr for handle 0x7f0889c13000, return Addr = 0x7f084270a7b8 ************ TIDL_subgraphRtCreate done ************ tidl_tfLiteRtImport_delegate.cpp Invoke 526 ******* In TIDL_subgraphRtInvoke ******** TIDL_process is started with handle : 0x7f0889c13000 TIDL_activate is called with handle : 0x7f0889c13000 - Copying handle of size 19736 from 0x7f0889c13000 to 0x7f08889cb080 Core 0 Alg Process for Layer # - 0, layer type 0 Core 0 Alg Process for Layer # - 1, layer type 29 Processing Layer # - 1 Core 0 End of Layer # - 1 with outPtrs[0] = 0x7f08872f5000 Core 0 Alg Process for Layer # - 2, layer type 1 Processing Layer # - 2 Core 0 End of Layer # - 2 with outPtrs[0] = 0x7f088738ab00 Core 0 Alg Process for Layer # - 3, layer type 1 Processing Layer # - 3 Core 0 End of Layer # - 3 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 4, layer type 1 Processing Layer # - 4 Core 0 End of Layer # - 4 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 5, layer type 1 Processing Layer # - 5 Core 0 End of Layer # - 5 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 6, layer type 1 Processing Layer # - 6 Core 0 End of Layer # - 6 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 7, layer type 1 Processing Layer # - 7 Core 0 End of Layer # - 7 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 8, layer type 1 Processing Layer # - 8 Core 0 End of Layer # - 8 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 9, layer type 1 Processing Layer # - 9 Core 0 End of Layer # - 9 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 10, layer type 1 Processing Layer # - 10 Core 0 End of Layer # - 10 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 11, layer type 1 Processing Layer # - 11 Core 0 End of Layer # - 11 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 12, layer type 1 Processing Layer # - 12 Core 0 End of Layer # - 12 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 13, layer type 1 Processing Layer # - 13 Core 0 End of Layer # - 13 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 14, layer type 1 Processing Layer # - 14 Core 0 End of Layer # - 14 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 15, layer type 1 Processing Layer # - 15 Core 0 End of Layer # - 15 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 16, layer type 1 Processing Layer # - 16 Core 0 End of Layer # - 16 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 17, layer type 1 Processing Layer # - 17 Core 0 End of Layer # - 17 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 18, layer type 1 Processing Layer # - 18 Core 0 End of Layer # - 18 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 19, layer type 1 Processing Layer # - 19 Core 0 End of Layer # - 19 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 20, layer type 1 Processing Layer # - 20 Core 0 End of Layer # - 20 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 21, layer type 1 Processing Layer # - 21 Core 0 End of Layer # - 21 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 22, layer type 1 Processing Layer # - 22 Core 0 End of Layer # - 22 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 23, layer type 1 Processing Layer # - 23 Core 0 End of Layer # - 23 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 24, layer type 1 Processing Layer # - 24 Core 0 End of Layer # - 24 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 25, layer type 1 Processing Layer # - 25 Core 0 End of Layer # - 25 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 26, layer type 1 Processing Layer # - 26 Core 0 End of Layer # - 26 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 27, layer type 1 Processing Layer # - 27 Core 0 End of Layer # - 27 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 28, layer type 1 Processing Layer # - 28 Core 0 End of Layer # - 28 with outPtrs[0] = 0x7f08879d5c80 Core 0 Alg Process for Layer # - 29, layer type 2 Processing Layer # - 29 Core 0 End of Layer # - 29 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 30, layer type 1 Processing Layer # - 30 Core 0 End of Layer # - 30 with outPtrs[0] = 0x7f08879d5c80 Core 0 Alg Process for Layer # - 31, layer type 29 Processing Layer # - 31 Core 0 End of Layer # - 31 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 32, layer type 38 Processing Layer # - 32 Core 0 End of Layer # - 32 with outPtrs[0] = 0x7f08879d5c80 Core 0 Alg Process for Layer # - 33, layer type 29 Processing Layer # - 33 Core 0 End of Layer # - 33 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 34, layer type 7 Processing Layer # - 34 Core 0 End of Layer # - 34 with outPtrs[0] = 0x7f088d174000 Core 0 Alg Process for Layer # - 35, layer type 0 TIDL_process is completed with handle : 0x7f0889c13000 Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, RestoreCycles,Multic7xContextCopyCycles, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 22, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Sum of Layer Cycles 0 Sub Graph Stats 1064.000000 1009098.000000 2141.000000 ******* TIDL_subgraphRtInvoke done ******** ************ Frame index 1 : Running float inference **************** tidl_tfLiteRtImport_delegate.cpp Invoke 647 tidl_tfLiteRtImport_delegate.cpp Invoke 526 ******* In TIDL_subgraphRtInvoke ******** TIDL_process is started with handle : 0x7f0889c13000 Core 0 Alg Process for Layer # - 0, layer type 0 Core 0 Alg Process for Layer # - 1, layer type 29 Processing Layer # - 1 Core 0 End of Layer # - 1 with outPtrs[0] = 0x7f08872f5000 Core 0 Alg Process for Layer # - 2, layer type 1 Processing Layer # - 2 Core 0 End of Layer # - 2 with outPtrs[0] = 0x7f088738ab00 Core 0 Alg Process for Layer # - 3, layer type 1 Processing Layer # - 3 Core 0 End of Layer # - 3 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 4, layer type 1 Processing Layer # - 4 Core 0 End of Layer # - 4 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 5, layer type 1 Processing Layer # - 5 Core 0 End of Layer # - 5 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 6, layer type 1 Processing Layer # - 6 Core 0 End of Layer # - 6 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 7, layer type 1 Processing Layer # - 7 Core 0 End of Layer # - 7 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 8, layer type 1 Processing Layer # - 8 Core 0 End of Layer # - 8 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 9, layer type 1 Processing Layer # - 9 Core 0 End of Layer # - 9 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 10, layer type 1 Processing Layer # - 10 Core 0 End of Layer # - 10 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 11, layer type 1 Processing Layer # - 11 Core 0 End of Layer # - 11 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 12, layer type 1 Processing Layer # - 12 Core 0 End of Layer # - 12 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 13, layer type 1 Processing Layer # - 13 Core 0 End of Layer # - 13 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 14, layer type 1 Processing Layer # - 14 Core 0 End of Layer # - 14 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 15, layer type 1 Processing Layer # - 15 Core 0 End of Layer # - 15 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 16, layer type 1 Processing Layer # - 16 Core 0 End of Layer # - 16 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 17, layer type 1 Processing Layer # - 17 Core 0 End of Layer # - 17 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 18, layer type 1 Processing Layer # - 18 Core 0 End of Layer # - 18 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 19, layer type 1 Processing Layer # - 19 Core 0 End of Layer # - 19 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 20, layer type 1 Processing Layer # - 20 Core 0 End of Layer # - 20 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 21, layer type 1 Processing Layer # - 21 Core 0 End of Layer # - 21 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 22, layer type 1 Processing Layer # - 22 Core 0 End of Layer # - 22 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 23, layer type 1 Processing Layer # - 23 Core 0 End of Layer # - 23 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 24, layer type 1 Processing Layer # - 24 Core 0 End of Layer # - 24 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 25, layer type 1 Processing Layer # - 25 Core 0 End of Layer # - 25 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 26, layer type 1 Processing Layer # - 26 Core 0 End of Layer # - 26 with outPtrs[0] = 0x7f08876a8d80 Core 0 Alg Process for Layer # - 27, layer type 1 Processing Layer # - 27 Core 0 End of Layer # - 27 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 28, layer type 1 Processing Layer # - 28 Core 0 End of Layer # - 28 with outPtrs[0] = 0x7f08879d5c80 Core 0 Alg Process for Layer # - 29, layer type 2 Processing Layer # - 29 Core 0 End of Layer # - 29 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 30, layer type 1 Processing Layer # - 30 Core 0 End of Layer # - 30 with outPtrs[0] = 0x7f08879d5c80 Core 0 Alg Process for Layer # - 31, layer type 29 Processing Layer # - 31 Core 0 End of Layer # - 31 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 32, layer type 38 Processing Layer # - 32 Core 0 End of Layer # - 32 with outPtrs[0] = 0x7f08879d5c80 Core 0 Alg Process for Layer # - 33, layer type 29 Processing Layer # - 33 Core 0 End of Layer # - 33 with outPtrs[0] = 0x7f0887520d00 Core 0 Alg Process for Layer # - 34, layer type 7 Processing Layer # - 34 Core 0 End of Layer # - 34 with outPtrs[0] = 0x7f088d174000 Core 0 Alg Process for Layer # - 35, layer type 0 TIDL_process is completed with handle : 0x7f0889c13000 Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, RestoreCycles,Multic7xContextCopyCycles, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 22, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Sum of Layer Cycles 0 Sub Graph Stats 190.000000 971528.000000 2140.000000 ******* TIDL_subgraphRtInvoke done ******** ************ Frame index 2 : Running fixed point mode for calibration **************** In TIDL_runtimesPostProcessNet -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 5]: ------------------ [TIDL Import] ERROR: Failed to run calibration pass, system command returned error: 132 -- [tidl_import_core.cpp, 678] [TIDL Import] ERROR: Failed to run Calibration - Failed in function: tidlRunQuantStatsTool -- [tidl_import_core.cpp, 1746] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_quantStatsFixedOrFloat -- [tidl_import_quantize.cpp, 3992] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_runIterativeCalibration -- [tidl_import_quantize.cpp, 4313] [TIDL Import] [QUANTIZATION] ERROR: - Failed in function: TIDL_import_quantize -- [tidl_import_quantize.cpp, 5195] [TIDL Import] ERROR: - Failed in function: TIDL_import_backend -- [tidl_import_core.cpp, 4428] [TIDL Import] ERROR: - Failed in function: TIDL_runtimesPostProcessNet -- [tidl_runtimes_import_common.cpp, 1414] tidl_tfLiteRtImport_delegate.cpp Invoke 647 Completed_Model : 1, Name : cl-0000_tflitert_imagenet1k_mlperf_mobilenet_v1_1.0_224_tflite, Total time : 3092.02, Offload Time : 0.00 , DDR RW MBs : 18446744073709.55, Output Image File : py_out_cl-0000_tflitert_imagenet1k_mlperf_mobilenet_v1_1.0_224_tflite_ADE_val_00001801.jpg, Output Bin File : py_out_cl-0000_tflitert_imagenet1k_mlperf_mobilenet_v1_1.0_224_tflite_ADE_val_00001801.bin ************ in TIDL_subgraphRtDelete ************ TIDL_deactivate is called with handle : 0x7f0889c13000 - Copying handle of size 19736 from 0x7f08889cb080 to 0x7f0889c13000 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 68565333 bytes MEM: Free's : 26 free's of 68565333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!