// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; #include "am33xx.dtsi" / { model = "TI AM335x BeagleTest"; compatible = "ti,am335x-bone", "ti,am33xx"; cpus { cpu@0 { cpu0-supply = <&vdd1_reg>; }; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; chosen { stdout-path = &uart0; tick-timer = &timer2; }; // vmmcsd_fixed: fixedregulator0 { // compatible = "regulator-fixed"; // regulator-name = "vmmcsd_fixed"; // regulator-min-microvolt = <3300000>; // regulator-max-microvolt = <3300000>; // regulator-boot-on; // }; vbat: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; }; sound_out: sound-out { compatible = "ont,on20-o2nm-out"; ti,model = "Opner O2NM Audio out"; ti,audio-codec = <&tas5508c>; ti,mcasp-controller = <&mcasp0>; ti,codec-clock-rate = <24576000>; }; pcm1808: pcm1808 { compatible = "ti,pcm1808"; }; sound_in: sound-in { compatible = "ont,on20-o2nm-in"; ti,model = "Opner O2NM Audio in"; ti,audio-codec = <&pcm1808>; ti,mcasp-controller = <&mcasp1>; ti,codec-clock-rate = <24576000>; }; }; // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < AM33XX_PADCONF(0x978,PIN_INPUT_PULLUP , MUX_MODE3) /* uart1_ctsn.i2c1_sda */ AM33XX_PADCONF(0x97c,PIN_INPUT_PULLUP , MUX_MODE3) /* uart1_rtsn.i2c1_scl */ /* TAS5508c reset */ AM33XX_PADCONF(0x8a4,PIN_OUTPUT , MUX_MODE7) /* lcd_data1.gpio2_7 */ /* LPC reset */ AM33XX_PADCONF(0x8d4,PIN_OUTPUT , MUX_MODE7) /* lcd_data13.gpio0_9 */ /* WD delay/beeper */ AM33XX_PADCONF(0x918,PIN_OUTPUT , MUX_MODE7) /* gmii1_rxdv.gpio3_4 */ /* LPC1768 i2c interrupt line */ AM33XX_PADCONF(0x8c0,PIN_INPUT_PULLUP , MUX_MODE7) /* lcd_data8.gpio2_14 */ >; }; mcasp0_pins: pinmux_mcasp0_pins { pinctrl-single,pins = < AM33XX_PADCONF(0x9ac,PIN_INPUT_PULLUP , MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */ AM33XX_PADCONF(0x990,PIN_OUTPUT_PULLUP , MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ AM33XX_PADCONF(0x994,PIN_OUTPUT_PULLUP , MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ AM33XX_PADCONF(0x998,PIN_OUTPUT_PULLUP , MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ AM33XX_PADCONF(0x9a8,PIN_OUTPUT_PULLUP , MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ AM33XX_PADCONF(0x9a0,PIN_OUTPUT_PULLUP , MUX_MODE2) /* mcasp0_aclkr.mcasp0_axr2 */ AM33XX_PADCONF(0x9a4,PIN_OUTPUT_PULLUP , MUX_MODE2) /* mcasp0_fsr.mcasp0_axr3 */ >; }; mcasp1_pins: pinmux_mcasp1_pins { pinctrl-single,pins = < AM33XX_PADCONF(0x940,PIN_INPUT_PULLUP , MUX_MODE4) /* gmii1_rxd0.mcasp1_ahclkr */ AM33XX_PADCONF(0x928,PIN_OUTPUT_PULLUP , MUX_MODE4) /* gmii1_txd0.mcasp1_aclkr */ AM33XX_PADCONF(0x93c,PIN_OUTPUT_PULLUP , MUX_MODE4) /* gmii1_rxd1.mcasp1_fsr */ AM33XX_PADCONF(0x914,PIN_INPUT_PULLUP , MUX_MODE4) /* gmii1_txen.mcasp1_axr0 */ AM33XX_PADCONF(0x924,PIN_INPUT_PULLUP , MUX_MODE4) /* gmii1_txd1.mcasp1_axr1 */ >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < AM33XX_PADCONF(0x950,PIN_INPUT_PULLDOWN,MUX_MODE0) /* spi0_sclk.spi0_sclk*/ AM33XX_PADCONF(0x954,PIN_INPUT_PULLUP,MUX_MODE0) /* spi0_d0.spi0_d0 */ AM33XX_PADCONF(0x958,PIN_INPUT_PULLDOWN,MUX_MODE0) /* spi0_d1.spi0_d1 */ AM33XX_PADCONF(0x95c,PIN_INPUT_PULLUP,MUX_MODE0) /* spi0_cs0.spi0_cs0 */ /* Interrupt from KZS8895 */ AM33XX_PADCONF(0x92c,PIN_INPUT_PULLUP,MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ /* Reset to KZS8895 */ AM33XX_PADCONF(0x930,PIN_OUTPUT,MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < AM33XX_PADCONF(0x800,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ AM33XX_PADCONF(0x804,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ AM33XX_PADCONF(0x808,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ AM33XX_PADCONF(0x80c,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ AM33XX_PADCONF(0x810,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ AM33XX_PADCONF(0x814,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ AM33XX_PADCONF(0x818,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ AM33XX_PADCONF(0x81c,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ AM33XX_PADCONF(0x820,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */ AM33XX_PADCONF(0x824,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */ AM33XX_PADCONF(0x828,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */ AM33XX_PADCONF(0x82c,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */ AM33XX_PADCONF(0x830,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */ AM33XX_PADCONF(0x834,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */ AM33XX_PADCONF(0x838,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */ AM33XX_PADCONF(0x83c,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */ AM33XX_PADCONF(0x870,PIN_INPUT_PULLUP , MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ AM33XX_PADCONF(0x874,PIN_INPUT_PULLUP , MUX_MODE7) /* gpmc_wpn.gpio0_30 */ AM33XX_PADCONF(0x87c,PIN_OUTPUT , MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ AM33XX_PADCONF(0x890,PIN_OUTPUT , MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ AM33XX_PADCONF(0x894,PIN_OUTPUT , MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ AM33XX_PADCONF(0x898,PIN_OUTPUT , MUX_MODE0) /* gpmc_wen.gpmc_wen */ AM33XX_PADCONF(0x89c,PIN_OUTPUT , MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; mii2_pins: pinmux_mii2_pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(0x840, PIN_OUTPUT, MUX_MODE1) /* mii1_txen.rgmii1_tctl */ AM33XX_PADCONF(0x844, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxdv.rgmii1_rctl */ AM33XX_PADCONF(0x848, PIN_OUTPUT, MUX_MODE1) /* mii1_txd3.rgmii1_td3 */ AM33XX_PADCONF(0x84c, PIN_OUTPUT, MUX_MODE1) /* mii1_txd2.rgmii1_td2 */ AM33XX_PADCONF(0x850, PIN_OUTPUT, MUX_MODE1) /* mii1_txd1.rgmii1_td1 */ AM33XX_PADCONF(0x854, PIN_OUTPUT, MUX_MODE1) /* mii1_txd0.rgmii1_td0 */ AM33XX_PADCONF(0x858, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_txclk.rgmii1_tclk */ AM33XX_PADCONF(0x85c, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxclk.rgmii1_rclk */ AM33XX_PADCONF(0x860, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd3.rgmii1_rd3 */ AM33XX_PADCONF(0x864, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.rgmii1_rd2 */ AM33XX_PADCONF(0x868, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd1.rgmii1_rd1 */ AM33XX_PADCONF(0x86c, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd0.rgmii1_rd0 */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; &usb0 { dr_mode = "peripheral"; interrupts-extended = <&intc 18 &tps 0>; interrupt-names = "mc", "vbus"; }; &usb1 { dr_mode = "host"; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; clock-frequency = <100000>; tps: tps@2D { reg = <0x2D>; }; baseboard_eeprom: baseboard_eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; }; }; &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <400000>; tas5508c: tas5508c@1b { compatible = "ti,tas5508c"; reg = <0x1b>; tas5508c,gpio_reset = <71>; /* gpio_reset = GPIO_TO_PIN(2,7) */ tas5508c,gpio_mute = <0>; }; ampinterface0: ampinterface0@60 { compatible = "ti,lpc1768"; reg = <0x60>; /* GPIO_TO_PIN(2,14) */ //ampinterface0,gpio_irq = <78>; // GPIO_TO_PIN(2,14) }; }; &spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; ti,pindir-d0-out-d1-in = <1>; ksz8895: ksz8895@0 { compatible = "micrel,ksz8895"; status = "okay"; spi-max-frequency = <12000000>; // spi-cpha; // spi-cpol; phy-mode = "mii"; reg = <0>; /* Chip select 0 */ ksz8895,gpio_reset = <74>; /* GPIO_TO_PIN(3,10) */ ksz8895,gpio_irq = <73>; /* GPIO_TO_PIN(3,9) */ // ports { // #address-cells = <1>; // #size-cells = <0>; // port@0 { // reg = <0>; // label = "lan1"; // }; // port@1 { // reg = <1>; // label = "lan2"; // }; // port@2 { // reg = <2>; // label = "lan3"; // }; // port@3 { // reg = <3>; // label = "lan4"; // }; // port@4 { // reg = <4>; // label = "cpu"; // ethernet = <&mac>; // phy-mode = "mii"; // fixed-link { // speed = <100>; // full-duplex; // }; // }; // }; }; }; &mac { status = "okay"; // phy-mode = "mii"; //#address-cells = <1>; //#size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mii2_pins>; dual_emac ; // fixed-link { // speed = <100>; // full-duplex; // }; }; &cpsw_emac0 { phy-mode = "mii"; dual_emac_res_vlan = <2>; fixed-link { speed = <100>; full-duplex; }; }; &cpsw_emac1 { phy-mode = "mii"; dual_emac_res_vlan = <3>; fixed-link { speed = <100>; full-duplex; }; }; // &davinci_mdio{ // status = "okay"; // }; //&mac_sw //{ // pinctrl-names = "default"; // pinctrl-0 = <&mii2_pins>; // status = "okay"; //}; &elm{ status = "okay"; }; &gpmc { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins_s0>; ranges = <0 0 0x08000000 0x10000000>; /* CS0: 16MB for NAND */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <40>; gpmc,oe-on-ns = <0>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,wait-on-read = "true"; gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x00020000>; }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00020000 0x00020000>; }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00040000 0x00020000>; }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x00060000 0x00020000>; }; partition@4 { label = "NAND.u-boot-spl-os"; reg = <0x00080000 0x00040000>; }; partition@5 { label = "NAND.u-boot"; reg = <0x000C0000 0x00100000>; }; partition@6 { label = "NAND.u-boot-env"; reg = <0x001C0000 0x00020000>; }; partition@7 { label = "NAND.u-boot-env.backup1"; reg = <0x001E0000 0x00020000>; }; partition@8 { label = "NAND.kernel"; reg = <0x00200000 0x00800000>; }; partition@9 { label = "NAND.file-system"; reg = <0x00A00000 0x0F600000>; }; }; }; /include/ "tps65910.dtsi" &tps { ti,en-ck32k-xtal = "true"; vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; vcc3-supply = <&vbat>; vcc4-supply = <&vbat>; vcc5-supply = <&vbat>; vcc6-supply = <&vbat>; vcc7-supply = <&vbat>; vccio-supply = <&vbat>; regulators { vrtc_reg: regulator@0 { regulator-always-on; }; vio_reg: regulator@1 { regulator-always-on; }; vdd1_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1312500>; regulator-boot-on; regulator-always-on; }; vdd2_reg: regulator@3 { /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; vdd3_reg: regulator@4 { regulator-always-on; }; vdig1_reg: regulator@5 { regulator-always-on; }; vdig2_reg: regulator@6 { regulator-always-on; }; vpll_reg: regulator@7 { regulator-always-on; }; vdac_reg: regulator@8 { regulator-always-on; }; vaux1_reg: regulator@9 { regulator-always-on; }; vaux2_reg: regulator@10 { regulator-always-on; }; vaux33_reg: regulator@11 { regulator-always-on; }; vmmc_reg: regulator@12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; &mmc1 { status = "okay"; bus-width = <0x4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vmmc_reg>; cd-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; }; &aes { status = "okay"; }; &sham { status = "okay"; }; &rtc { status = "disabled"; ti,hwmods="disabled"; }; &mcasp0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcasp0_pins>; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializers */ num-serializer = <4>; serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1 1 1 1 >; tx-num-evt = <1>; rx-num-evt = <1>; }; &mcasp1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcasp1_pins>; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 2 serializers */ num-serializer = <2>; serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 2 2 >; tx-num-evt = <1>; rx-num-evt = <1>; };