--- original_dp83869.c
+++ edited_dp83869.c
@@ -167,8 +167,13 @@
 			if (dp83869->mode == DP83869_RGMII_100_BASE)
 				phydev->speed = SPEED_100;
 		} else {
+			#if 1
 			phydev->speed = SPEED_UNKNOWN;
 			phydev->duplex = DUPLEX_UNKNOWN;
+			#else //Added for testing
+			phydev->speed = SPEED_1000;
+			phydev->duplex = DUPLEX_FULL;
+			#endif
 		}
 	}
 
@@ -650,26 +655,69 @@
 	if (dp83869->mode == DP83869_RGMII_1000_BASE) {
 		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 				 phydev->supported);
+		 #if 0 // Added for testig
+		 //phydev->speed = SPEED_1000;
+		 #else
+		 //phy_write(phydev, MII_BMCR, 0x0140);
+		 #endif
 	} else {
 		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
 				 phydev->supported);
 		linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
 				 phydev->supported);
-
-		/* Auto neg is not supported in 100base FX mode */
+		#if 0 // Added for testig
+		 //phydev->speed = SPEED_100;
+		#endif
+	}
+
+	/* Auto neg is not supported in 100base FX mode */
+	bmcr = phy_read(phydev, MII_BMCR);
+	if (bmcr < 0)
+		return bmcr;
+
+	#if 1
+	phydev->autoneg = AUTONEG_DISABLE;
+	#endif
+	
+	#if 1
+	linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
+	linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising);
+	#endif
+
+	if (bmcr & BMCR_ANENABLE) {
+	
+		#if 0
+		ret =  phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
+		if (ret < 0)
+			return ret;
+		
+		#if 1 //Added for test
 		bmcr = phy_read(phydev, MII_BMCR);
-		if (bmcr < 0)
-			return bmcr;
-
-		phydev->autoneg = AUTONEG_DISABLE;
-		linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
-		linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising);
-
-		if (bmcr & BMCR_ANENABLE) {
-			ret =  phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
-			if (ret < 0)
-				return ret;
-		}
+		printk(KERN_ERR "dp83869: 1.bmcr: %x\n", bmcr);
+		#endif
+
+		if(dp83869->mode == DP83869_RGMII_1000_BASE){
+		#if 1 //Added for test
+			printk(KERN_ERR "dp83869: Setting speed 1000 - 0x%x\n", BMCR_SPEED1000);
+			ret =  phy_modify(phydev, MII_BMCR, BMCR_SPEED1000, 1);
+		#endif
+		}else {
+		#if 1 //Added for test
+			printk(KERN_ERR "dp83869: Setting speed 100 - 0x%x\n", BMCR_SPEED100);
+			ret =  phy_modify(phydev, MII_BMCR, BMCR_SPEED100, 1);
+		#endif
+		}
+		#else /* Added for test */
+		ret = phy_write(phydev, MII_BMCR, 0x0140);
+		printk(KERN_ERR "dp83869: Writing directly 0x0140\n");
+		#endif
+		if (ret < 0)
+			return ret;	
+		
+		#if 1 /* Added for test */
+		bmcr = phy_read(phydev, MII_BMCR);
+		printk(KERN_ERR "dp83869: 2.bmcr: 0x%x\n", bmcr);
+		#endif 
 	}
 
 	/* Update advertising from supported */
@@ -696,6 +744,9 @@
 	if (phydev->interface == PHY_INTERFACE_MODE_MII) {
 		if (dp83869->mode == DP83869_100M_MEDIA_CONVERT ||
 		    dp83869->mode == DP83869_RGMII_100_BASE ||
+#if 0
+		    dp83869->mode == DP83869_RGMII_1000_BASE ||
+#endif
 		    dp83869->mode == DP83869_RGMII_COPPER_ETHERNET) {
 			phy_ctrl_val |= DP83869_OP_MODE_MII;
 		} else {
@@ -709,9 +760,16 @@
 	if (ret)
 		return ret;
 
+#if 0 // Added condition for testing
+	if(dp83869->mode != DP83869_RGMII_1000_BASE) 
+	{
+#endif
 	ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
 	if (ret)
 		return ret;
+#if 0 
+		}
+#endif
 
 	phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |
 			dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT |
@@ -731,6 +789,7 @@
 		ret = dp83869_configure_rgmii(phydev, dp83869);
 		if (ret)
 			return ret;
+		printk(KERN_ERR "dp83869: Copper Ethernet\n");
 		break;
 	case DP83869_RGMII_SGMII_BRIDGE:
 		ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
@@ -780,6 +839,7 @@
 		break;
 	case DP83869_RGMII_1000_BASE:
 	case DP83869_RGMII_100_BASE:
+		printk(KERN_ERR "dp83869: Fiber Ethernet\n");
 		ret = dp83869_configure_fiber(phydev, dp83869);
 		break;
 	default:
@@ -798,11 +858,17 @@
 	ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,
 			 DP83869_DOWNSHIFT_EN);
 	if (ret)
+	{	
+		printk(KERN_ERR "dp83869: DP83869_DOWNSHIFT_EN\n");
 		return ret;
+		}
 
 	ret = dp83869_configure_mode(phydev, dp83869);
 	if (ret)
+	{
+		printk(KERN_ERR "dp83869: dp83869_configure_mode\n");
 		return ret;
+		}
 
 	/* Enable Interrupt output INT_OE in CFG4 register */
 	if (phy_interrupt_is_valid(phydev)) {
@@ -827,7 +893,10 @@
 				    dp83869->rx_int_delay |
 			dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT);
 		if (ret)
-			return ret;
+		{
+			printk(KERN_ERR "dp83869: phy_interface_is_rgmii\n");
+			return ret;
+			}
 
 		val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
 		val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
@@ -854,17 +923,25 @@
 {
 	struct dp83869_private *dp83869;
 	int ret;
-
+	printk(KERN_ERR "dp83869: Probing Started\n");
 	dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869),
 			       GFP_KERNEL);
+	printk(KERN_ERR "dp83869: Devaddr: %px\n", dp83869);
+	
 	if (!dp83869)
+	{
+		printk(KERN_ERR "dp83869: ENOMEM\n");
 		return -ENOMEM;
+		}
 
 	phydev->priv = dp83869;
 
 	ret = dp83869_of_init(phydev);
 	if (ret)
+	{
+		printk(KERN_ERR "dp83869: Init failed\n");
 		return ret;
+		}
 
 	if (dp83869->mode == DP83869_RGMII_100_BASE ||
 	    dp83869->mode == DP83869_RGMII_1000_BASE)
@@ -882,6 +959,7 @@
 		return ret;
 
 	usleep_range(10, 20);
+	
 
 	/* Global sw reset sets all registers to default.
 	 * Need to set the registers in the PHY to the right config.