/*
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra74x.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/pinmux/mux_dra7xx.h>

/ {
	model = "TI DRA742";
	compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
	
	memory {
		device_type = "memory";
		reg = <0x80000000 0x80000000>; /* 2048 MB */
		//reg = <0x80000000 0x40000000>; /* 1024 MB */	
	};

	reserved_mem: reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		ipu2_cma_pool: ipu2_cma@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x95800000 0x3800000>;
			reusable;
			status = "okay";
		};

		dsp1_cma_pool: dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x99000000 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_cma_pool: ipu1_cma@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x9d000000 0x2000000>;
			reusable;
			status = "okay";
		};

		dsp2_cma_pool: dsp2_cma@9f000000 {
			compatible = "shared-dma-pool";
			reg = <0x9f000000 0x800000>;
			reusable;
			status = "okay";
		};
	};

//	extcon_usb1: extcon_usb1 {
//	 	status = "disabled";
//		compatible = "linux,extcon-usb-gpio";
//		id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
//	};

//	extcon_usb2: extcon_usb2 {
//		status = "disabled";
//		compatible = "linux,extcon-usb-gpio";
//		id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
//	};

	evm_3v3_sd: fixedregulator-evm_3v3_sd {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	evm_3v3_sw: fixedregulator-evm_3v3_sw {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3_sw";
		vin-supply = <&sysen1>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		/* TPS77018DBVT */
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd";
		vin-supply = <&evm_3v3_sw>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	vmmcwl_fixed: fixedregulator-mmcwl {
		compatible = "regulator-fixed";
		regulator-name = "vmmcwl_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		//gpio = <&gpio5 8 0>;	/* gpio5_8 */
		startup-delay-us = <70000>;
		enable-active-high;
	};

/*
	kim {
		compatible = "kim";
		nshutdown_gpio = <132>;
		dev_name = "/dev/ttyS2";
		flow_cntrl = <1>;
		baud_rate = <3686400>;
	};

	btwilink {
		compatible = "btwilink";
	};
*/

	vtt_fixed: fixedregulator-vtt {
		compatible = "regulator-fixed";
		regulator-name = "vtt_fixed";
		regulator-min-microvolt = <1350000>;
		regulator-max-microvolt = <1350000>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&sysen2>;
		//gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
	};

	aliases {
		display0 = &hdmi0;
		sound0 = &primary_sound;
		sound1 = &hdmi;
	};

	hdmi0: connector@1 {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "a";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&tpd12s015_out>;
			};
		};
	};

	tpd12s015: encoder@1 {
		compatible = "ti,dra7evm-tpd12s015";

		pinctrl-names = "i2c", "ddc";
		pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
		pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;

		ddc-i2c-bus = <&i2c2>;
		mcasp-gpio = <&mcasp8>;

		gpios = <&pcf_hdmi 4 0>,	/* P4, CT CP HPD */
			<&pcf_hdmi 5 0>,	/* P5, LS OE */
			<&gpio7 12 0>;	/* gpio7_12/sp1_cs2, HPD */

		//disable-hpd;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tpd12s015_in: endpoint@0 {
					remote-endpoint = <&hdmi_out>;
				};
			};

			port@1 {
				reg = <1>;

				tpd12s015_out: endpoint@0 {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};

    ocp {
        gpu: gpu@0x56000000 {
            gpu0-voltdm = <&voltdm_gpu>;
        };
    };


	primary_sound: primary_sound {
		compatible = "ti,dra7xx-evm-audio";
		ti,model = "DRA7xx-EVM";
		ti,always-on;
		ti,audio-codec = <&tlv320aic3106>;
		ti,mcasp-controller = <&mcasp3>;
		ti,codec-clock-rate = <11289600>;
		clocks = <&atl_clkin2_ck>;
		clock-names = "mclk";
		ti,audio-routing =
			"Headphone Jack",       "HPLOUT",
			"Headphone Jack",       "HPROUT",
			"Line Out",		"LLOUT",
			"Line Out",		"RLOUT",
			"MIC3L",		"Mic Jack",
			"MIC3R",		"Mic Jack",
			"Mic Jack",		"Mic Bias",
			"LINE1L",               "Line In",
			"LINE1R",               "Line In";
	};

	btwilink_sound: btwilink_sound {
		#sound-dai-cells = <0>;
		compatible = "linux,bt-sco-audio";
		status = "okay";
	};

	simple_bt_sco_card: bt_sco_card {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-WiLink";
		simple-audio-card,format = "dsp_a";
		simple-audio-card,frame-master = <&btwilink_codec>;
		simple-audio-card,bitclock-master = <&btwilink_codec>;
		simple-audio-card,frame-inversion;

		simple-audio-card,cpu {
			sound-dai = <&mcasp7>;
		};

		btwilink_codec: simple-audio-card,codec {
			sound-dai = <&btwilink_sound>;
		};
	};
};

&dra7_pmx_core {

	uart1_pins: pinmux_uart1_pins {
		pinctrl-single,pins = <

			// i2c_3		
			GPMC_ADVN_ALE (PIN_INPUT | MUX_MODE8)	/* gpmc_advn_ale.i2c3_sda -> 8 */
			GPMC_CLK      (PIN_INPUT | MUX_MODE8)	/* gpmc_clk.i2c3_scl -> 8 */		
			// i2c_4	
			MMC1_SDCD (PIN_INPUT | MUX_MODE4)  		/* mmc1_sdcd.i2c4_sda -> 4 */
			MMC1_SDWP (PIN_INPUT | MUX_MODE4)  		/* mmc1_sdwp.i2c4_scl -> 4 */		
			// i2c_5	
			MCASP1_AXR0 (PIN_INPUT | MUX_MODE10)	/* mcasp1_axr0.i2c5_sda -> 10 */
			MCASP1_AXR1 (PIN_INPUT | MUX_MODE10)	/* mcasp1_axr1.i2c5_scl -> 10 */	
	
			// spi 1.0, 1.1, 1.3
			SPI1_SCLK	(PIN_INPUT | MUX_MODE0)	/*	0x3A4	*/
			SPI1_D1		(PIN_INPUT | MUX_MODE0)	/*	0x3A8	*/
			SPI1_D0		(PIN_INPUT | MUX_MODE0)	/*	0x3AC	*/
			SPI1_CS0	(PIN_INPUT | MUX_MODE0)	/*	0x3B0	*/
			SPI1_CS1	(PIN_INPUT | MUX_MODE0)	/*	0x3B4	*/
			SPI1_CS3	(PIN_INPUT | MUX_MODE0)	/*	0x3BC	*/
	
			// spi 2.0
			SPI2_SCLK	( PIN_INPUT | MUX_MODE0 )	/*	0x3C0	*/
			SPI2_D1		( PIN_INPUT | MUX_MODE0 )	/*	0x3C4	*/
			SPI2_D0		( PIN_INPUT | MUX_MODE0 )	/*	0x3C8	*/
			SPI2_CS0	( PIN_INPUT | MUX_MODE0 )	/*	0x3CC	*/

			// spi 3.0
			VOUT1_CLK		(PIN_INPUT | MUX_MODE8)	// DAB_SPI_CS		GPIO4_19
			VOUT1_DE		(PIN_INPUT | MUX_MODE8)	// DAB_SPI_MISO	GPIO4_20
			VOUT1_HSYNC	(PIN_INPUT | MUX_MODE8)	// DAB_SPI_MOSI	GPIO4_22
			VOUT1_VSYNC	(PIN_INPUT | MUX_MODE8)	// DAB_SPI_SCK		GPIO4_23	
			
			// BT656 vin4b
			MDIO_MCLK	(PIN_INPUT | MUX_MODE5)		/*	0x23C	*/	// BT656_CLK1
			MDIO_D	(PIN_INPUT | MUX_MODE5)		/*	0x240	*/		// BT656_DO
			UART3_RXD	(PIN_INPUT | MUX_MODE5)	/*	0x248	*/		// BT656_D1
			UART3_TXD	(PIN_INPUT | MUX_MODE5)	/*	0x24C	*/		// BT656_D2
			RGMII0_TXC	(PIN_INPUT | MUX_MODE5)	/*	0x250	*/	// BT656_D3
			RGMII0_TXCTL	(PIN_INPUT | MUX_MODE5)	/*	0x254	*/	// BT656_D4
			RGMII0_RXC	(PIN_INPUT | MUX_MODE5)	/*	0x268	*/		// BT656_D5
			RGMII0_RXCTL	(PIN_INPUT | MUX_MODE5)	/*	0x26C	*/	// BT656_D6	
			RGMII0_RXD3	(PIN_INPUT | MUX_MODE5)	/*	0x270	*/		// BT656_D7

			RGMII0_RXD2	(PIN_INPUT | MUX_MODE14)	/*	0x274	*/
			VIN2A_DE0	(PIN_INPUT | MUX_MODE14)	/*	0x158	*/

//===================================================================================

		//GPMC_AD0	(PIN_INPUT | MUX_MODE14)	/*	0x000	*/
		//GPMC_AD1	(PIN_INPUT | MUX_MODE14)	/*	0x004	*/
		//GPMC_AD2	(PIN_INPUT | MUX_MODE14)	/*	0x008	*/
		//GPMC_AD3	(PIN_INPUT | MUX_MODE14)	/*	0x00C	*/
		//GPMC_AD4	(PIN_INPUT | MUX_MODE14)	/*	0x010	*/
		//GPMC_AD5	(PIN_INPUT | MUX_MODE14)	/*	0x014	*/
		//GPMC_AD6	(PIN_INPUT | MUX_MODE14)	/*	0x018	*/
		//GPMC_AD7	(PIN_INPUT | MUX_MODE14)	/*	0x01C	*/
		//GPMC_AD8	(PIN_INPUT | MUX_MODE14)	/*	0x020	*/
		//GPMC_AD9	(PIN_INPUT | MUX_MODE14)	/*	0x024	*/
		//GPMC_AD10	(PIN_INPUT | MUX_MODE14)	/*	0x028	*/
		//GPMC_AD11	(PIN_INPUT | MUX_MODE14)	/*	0x02C	*/
		//GPMC_AD12	(PIN_INPUT | MUX_MODE14)	/*	0x030	*/
		//GPMC_AD13	(PIN_INPUT | MUX_MODE14)	/*	0x034	*/
		//GPMC_AD14	(PIN_INPUT | MUX_MODE14)	/*	0x038	*/
		//GPMC_AD15	(PIN_INPUT | MUX_MODE14)	/*	0x03C	*/
		//GPMC_A0	(PIN_INPUT | MUX_MODE14)	/*	0x040	*/
		//GPMC_A1	(PIN_INPUT | MUX_MODE14)	/*	0x044	*/
		//GPMC_A2	(PIN_INPUT | MUX_MODE14)	/*	0x048	*/
		//GPMC_A3	(PIN_INPUT | MUX_MODE14)	/*	0x04C	*/
		//GPMC_A4	(PIN_INPUT | MUX_MODE14)	/*	0x050	*/
		//GPMC_A5	(PIN_INPUT | MUX_MODE14)	/*	0x054	*/
		//GPMC_A6	(PIN_INPUT | MUX_MODE14)	/*	0x058	*/
		//GPMC_A7	(PIN_INPUT | MUX_MODE14)	/*	0x05C	*/
		//GPMC_A8	(PIN_INPUT | MUX_MODE14)	/*	0x060	*/
		//GPMC_A9	(PIN_INPUT | MUX_MODE14)	/*	0x064	*/
		//GPMC_A10	(PIN_INPUT | MUX_MODE14)	/*	0x068	*/
		//GPMC_A11	(PIN_INPUT | MUX_MODE14)	/*	0x06C	*/
		GPMC_A12	(PIN_INPUT | MUX_MODE14)	/*	0x070	*/
		GPMC_A13	(PIN_INPUT | MUX_MODE14)	/*	0x074	*/
		GPMC_A14	(PIN_INPUT | MUX_MODE14)	/*	0x078	*/
		GPMC_A15	(PIN_INPUT | MUX_MODE14)	/*	0x07C	*/
		GPMC_A16	(PIN_INPUT | MUX_MODE14)	/*	0x080	*/
		GPMC_A17	(PIN_INPUT | MUX_MODE14)	/*	0x084	*/
		GPMC_A18	(PIN_INPUT | MUX_MODE14)	/*	0x088	*/
		//GPMC_A19	(PIN_INPUT | MUX_MODE14)	/*	0x08C	*/
		//GPMC_A20	(PIN_INPUT | MUX_MODE14)	/*	0x090	*/
		//GPMC_A21	(PIN_INPUT | MUX_MODE14)	/*	0x094	*/
		//GPMC_A22	(PIN_INPUT | MUX_MODE14)	/*	0x098	*/
		//GPMC_A23	(PIN_INPUT | MUX_MODE14)	/*	0x09C	*/
		//GPMC_A24	(PIN_INPUT | MUX_MODE14)	/*	0x0A0	*/
		//GPMC_A25	(PIN_INPUT | MUX_MODE14)	/*	0x0A4	*/
		//GPMC_A26	(PIN_INPUT | MUX_MODE14)	/*	0x0A8	*/
		//GPMC_A27	(PIN_INPUT | MUX_MODE14)	/*	0x0AC	*/
		//GPMC_CS1	(PIN_INPUT | MUX_MODE14)	/*	0x0B0	*/
		GPMC_CS0	(PIN_INPUT | MUX_MODE14)	/*	0x0B4	*/
		GPMC_CS2	(PIN_INPUT | MUX_MODE14)	/*	0x0B8	*/
		//GPMC_CS3	(PIN_INPUT | MUX_MODE14)	/*	0x0BC	*/
		//GPMC_CLK	(PIN_INPUT | MUX_MODE14)	/*	0x0C0	*/
		//GPMC_ADVN_ALE	(PIN_INPUT | MUX_MODE14)	/*	0x0C4	*/
		GPMC_OEN_REN	(PIN_INPUT | MUX_MODE14)	/*	0x0C8	*/
		GPMC_WEN	(PIN_INPUT | MUX_MODE14)	/*	0x0CC	*/
		GPMC_BEN0	(PIN_INPUT | MUX_MODE14)	/*	0x0D0	*/
		GPMC_BEN1	(PIN_INPUT | MUX_MODE14)	/*	0x0D4	*/
		GPMC_WAIT0	(PIN_INPUT | MUX_MODE14)	/*	0x0D8	*/
		VIN1A_CLK0	(PIN_INPUT | MUX_MODE14)	/*	0x0DC	*/
		VIN1B_CLK1	(PIN_INPUT | MUX_MODE14)	/*	0x0E0	*/
		VIN1A_DE0	(PIN_INPUT | MUX_MODE14)	/*	0x0E4	*/
		VIN1A_FLD0	(PIN_INPUT | MUX_MODE14)	/*	0x0E8	*/
		VIN1A_HSYNC0	(PIN_INPUT | MUX_MODE14)	/*	0x0EC	*/
		VIN1A_VSYNC0	(PIN_INPUT | MUX_MODE14)	/*	0x0F0	*/
		VIN1A_D0	(PIN_INPUT | MUX_MODE14)	/*	0x0F4	*/
		VIN1A_D1	(PIN_INPUT | MUX_MODE14)	/*	0x0F8	*/
		VIN1A_D2	(PIN_INPUT | MUX_MODE14)	/*	0x0FC	*/
		VIN1A_D3	(PIN_INPUT | MUX_MODE14)	/*	0x100	*/
		VIN1A_D4	(PIN_INPUT | MUX_MODE14)	/*	0x104	*/
		VIN1A_D5	(PIN_INPUT | MUX_MODE14)	/*	0x108	*/
		VIN1A_D6	(PIN_INPUT | MUX_MODE14)	/*	0x10C	*/
		VIN1A_D7	(PIN_INPUT | MUX_MODE14)	/*	0x110	*/
		VIN1A_D8	(PIN_INPUT | MUX_MODE14)	/*	0x114	*/
		VIN1A_D9	(PIN_INPUT | MUX_MODE14)	/*	0x118	*/
		VIN1A_D10	(PIN_INPUT | MUX_MODE14)	/*	0x11C	*/
		VIN1A_D11	(PIN_INPUT | MUX_MODE14)	/*	0x120	*/
		VIN1A_D12	(PIN_INPUT | MUX_MODE14)	/*	0x124	*/
		VIN1A_D13	(PIN_INPUT | MUX_MODE14)	/*	0x128	*/
		VIN1A_D14	(PIN_INPUT | MUX_MODE14)	/*	0x12C	*/
		VIN1A_D15	(PIN_INPUT | MUX_MODE14)	/*	0x130	*/
		VIN1A_D16	(PIN_INPUT | MUX_MODE14)	/*	0x134	*/
		VIN1A_D17	(PIN_INPUT | MUX_MODE14)	/*	0x138	*/
		VIN1A_D18	(PIN_INPUT | MUX_MODE14)	/*	0x13C	*/
		VIN1A_D19	(PIN_INPUT | MUX_MODE14)	/*	0x140	*/
		VIN1A_D20	(PIN_INPUT | MUX_MODE14)	/*	0x144	*/
		VIN1A_D21	(PIN_INPUT | MUX_MODE14)	/*	0x148	*/
		VIN1A_D22	(PIN_INPUT | MUX_MODE14)	/*	0x14C	*/
		VIN1A_D23	(PIN_INPUT | MUX_MODE14)	/*	0x150	*/
		VIN2A_CLK0	(PIN_INPUT | MUX_MODE14)	/*	0x154	*/
//		VIN2A_DE0	(PIN_INPUT | MUX_MODE14)	/*	0x158	*/
		VIN2A_FLD0	(PIN_INPUT | MUX_MODE14)	/*	0x15C	*/
		VIN2A_HSYNC0	(PIN_INPUT | MUX_MODE14)	/*	0x160	*/
		VIN2A_VSYNC0	(PIN_INPUT | MUX_MODE14)	/*	0x164	*/
		VIN2A_D0	(PIN_INPUT | MUX_MODE14)	/*	0x168	*/
		VIN2A_D1	(PIN_INPUT | MUX_MODE14)	/*	0x16C	*/
		//VIN2A_D2	(PIN_INPUT | MUX_MODE14)	/*	0x170	*/
		//VIN2A_D3	(PIN_INPUT | MUX_MODE14)	/*	0x174	*/
		//VIN2A_D4	(PIN_INPUT | MUX_MODE14)	/*	0x178	*/
		//VIN2A_D5	(PIN_INPUT | MUX_MODE14)	/*	0x17C	*/
		VIN2A_D6	(PIN_INPUT | MUX_MODE14)	/*	0x180	*/
		VIN2A_D7	(PIN_INPUT | MUX_MODE14)	/*	0x184	*/
		//VIN2A_D8	(PIN_INPUT | MUX_MODE14)	/*	0x188	*/
		//VIN2A_D9	(PIN_INPUT | MUX_MODE14)	/*	0x18C	*/
		VIN2A_D10	(PIN_INPUT | MUX_MODE14)	/*	0x190	*/
		VIN2A_D11	(PIN_INPUT | MUX_MODE14)	/*	0x194	*/
		VIN2A_D12	(PIN_INPUT | MUX_MODE14)	/*	0x198	*/
		VIN2A_D13	(PIN_INPUT | MUX_MODE14)	/*	0x19C	*/
		VIN2A_D14	(PIN_INPUT | MUX_MODE14)	/*	0x1A0	*/
		VIN2A_D15	(PIN_INPUT | MUX_MODE14)	/*	0x1A4	*/
		VIN2A_D16	(PIN_INPUT | MUX_MODE14)	/*	0x1A8	*/
		VIN2A_D17	(PIN_INPUT | MUX_MODE14)	/*	0x1AC	*/
		VIN2A_D18	(PIN_INPUT | MUX_MODE14)	/*	0x1B0	*/
		VIN2A_D19	(PIN_INPUT | MUX_MODE14)	/*	0x1B4	*/
		VIN2A_D20	(PIN_INPUT | MUX_MODE14)	/*	0x1B8	*/
		VIN2A_D21	(PIN_INPUT | MUX_MODE14)	/*	0x1BC	*/
		VIN2A_D22	(PIN_INPUT | MUX_MODE14)	/*	0x1C0	*/
		VIN2A_D23	(PIN_INPUT | MUX_MODE14)	/*	0x1C4	*/
		//VOUT1_CLK	(PIN_INPUT | MUX_MODE14)	/*	0x1C8	*/
		//VOUT1_DE	(PIN_INPUT | MUX_MODE14)	/*	0x1CC	*/
		VOUT1_FLD	(PIN_INPUT | MUX_MODE14)	/*	0x1D0	*/
		//VOUT1_HSYNC	(PIN_INPUT | MUX_MODE14)	/*	0x1D4	*/
		//VOUT1_VSYNC	(PIN_INPUT | MUX_MODE14)	/*	0x1D8	*/
		//VOUT1_D0	(PIN_INPUT | MUX_MODE14)	/*	0x1DC	*/	// uart5
		//VOUT1_D1	(PIN_INPUT | MUX_MODE14)	/*	0x1E0	*/	// uart5
		VOUT1_D2	(PIN_INPUT | MUX_MODE14)	/*	0x1E4	*/
		VOUT1_D3	(PIN_INPUT | MUX_MODE14)	/*	0x1E8	*/
		VOUT1_D4	(PIN_INPUT | MUX_MODE14)	/*	0x1EC	*/
		VOUT1_D5	(PIN_INPUT | MUX_MODE14)	/*	0x1F0	*/
		VOUT1_D6	(PIN_INPUT | MUX_MODE14)	/*	0x1F4	*/
		VOUT1_D7	(PIN_INPUT | MUX_MODE14)	/*	0x1F8	*/
		//VOUT1_D8	(PIN_INPUT | MUX_MODE14)	/*	0x1FC	*/	// uart6
		//VOUT1_D9	(PIN_INPUT | MUX_MODE14)	/*	0x200	*/	// uart6
		VOUT1_D10	(PIN_INPUT | MUX_MODE14)	/*	0x204	*/
		VOUT1_D11	(PIN_INPUT | MUX_MODE14)	/*	0x208	*/
		VOUT1_D12	(PIN_INPUT | MUX_MODE14)	/*	0x20C	*/
		VOUT1_D13	(PIN_INPUT | MUX_MODE14)	/*	0x210	*/
		VOUT1_D14	(PIN_INPUT | MUX_MODE14)	/*	0x214	*/
		VOUT1_D15	(PIN_INPUT | MUX_MODE14)	/*	0x218	*/
		VOUT1_D16	(PIN_INPUT | MUX_MODE14)	/*	0x21C	*/
		VOUT1_D17	(PIN_INPUT | MUX_MODE14)	/*	0x220	*/
		VOUT1_D18	(PIN_INPUT | MUX_MODE14)	/*	0x224	*/
		VOUT1_D19	(PIN_INPUT | MUX_MODE14)	/*	0x228	*/
		VOUT1_D20	(PIN_INPUT | MUX_MODE14)	/*	0x22C	*/
		VOUT1_D21	(PIN_INPUT | MUX_MODE14)	/*	0x230	*/
		VOUT1_D22	(PIN_INPUT | MUX_MODE14)	/*	0x234	*/
		VOUT1_D23	(PIN_INPUT | MUX_MODE14)	/*	0x238	*/
//		MDIO_MCLK	(PIN_INPUT | MUX_MODE14)	/*	0x23C	*/
//		MDIO_D	(PIN_INPUT | MUX_MODE14)	/*	0x240	*/
		RMII_MHZ_50_CLK	(PIN_INPUT | MUX_MODE14)	/*	0x244	*/
//		UART3_RXD	(PIN_INPUT | MUX_MODE14)	/*	0x248	*/
//		UART3_TXD	(PIN_INPUT | MUX_MODE14)	/*	0x24C	*/
//		RGMII0_TXC	(PIN_INPUT | MUX_MODE14)	/*	0x250	*/
//		RGMII0_TXCTL	(PIN_INPUT | MUX_MODE14)	/*	0x254	*/
		RGMII0_TXD3	(PIN_INPUT | MUX_MODE14)	/*	0x258	*/
		RGMII0_TXD2	(PIN_INPUT | MUX_MODE14)	/*	0x25C	*/
		RGMII0_TXD1	(PIN_INPUT | MUX_MODE14)	/*	0x260	*/
		RGMII0_TXD0	(PIN_INPUT | MUX_MODE14)	/*	0x264	*/
//		RGMII0_RXC	(PIN_INPUT | MUX_MODE14)	/*	0x268	*/
//		RGMII0_RXCTL	(PIN_INPUT | MUX_MODE14)	/*	0x26C	*/
//		RGMII0_RXD3	(PIN_INPUT | MUX_MODE14)	/*	0x270	*/
//		RGMII0_RXD2	(PIN_INPUT | MUX_MODE14)	/*	0x274	*/
		RGMII0_RXD1	(PIN_INPUT | MUX_MODE14)	/*	0x278	*/
		RGMII0_RXD0	(PIN_INPUT | MUX_MODE14)	/*	0x27C	*/
		USB1_DRVVBUS	(PIN_INPUT | MUX_MODE14)	/*	0x280	*/
		USB2_DRVVBUS	(PIN_INPUT | MUX_MODE14)	/*	0x284	*/
		GPIO6_14	(PIN_INPUT | MUX_MODE14)	/*	0x288	*/
		GPIO6_15	(PIN_INPUT | MUX_MODE14)	/*	0x28C	*/
		GPIO6_16	(PIN_INPUT | MUX_MODE14)	/*	0x290	*/
		XREF_CLK0	(PIN_INPUT | MUX_MODE14)	/*	0x294	*/
		XREF_CLK1	(PIN_INPUT | MUX_MODE14)	/*	0x298	*/
		XREF_CLK2	(PIN_INPUT | MUX_MODE14)	/*	0x29C	*/
		XREF_CLK3	(PIN_INPUT | MUX_MODE14)	/*	0x2A0	*/
		MCASP1_ACLKX	(PIN_INPUT | MUX_MODE14)	/*	0x2A4	*/
		MCASP1_FSX	(PIN_INPUT | MUX_MODE14)	/*	0x2A8	*/
		MCASP1_ACLKR	(PIN_INPUT | MUX_MODE14)	/*	0x2AC	*/
		MCASP1_FSR	(PIN_INPUT | MUX_MODE14)	/*	0x2B0	*/
		//MCASP1_AXR0	(PIN_INPUT | MUX_MODE14)	/*	0x2B4	*/
		//MCASP1_AXR1	(PIN_INPUT | MUX_MODE14)	/*	0x2B8	*/
		MCASP1_AXR2	(PIN_INPUT | MUX_MODE14)	/*	0x2BC	*/
		MCASP1_AXR3	(PIN_INPUT | MUX_MODE14)	/*	0x2C0	*/
		MCASP1_AXR4	(PIN_INPUT | MUX_MODE14)	/*	0x2C4	*/
		MCASP1_AXR5	(PIN_INPUT | MUX_MODE14)	/*	0x2C8	*/
		MCASP1_AXR6	(PIN_INPUT | MUX_MODE14)	/*	0x2CC	*/
		MCASP1_AXR7	(PIN_INPUT | MUX_MODE14)	/*	0x2D0	*/
		MCASP1_AXR8	(PIN_INPUT | MUX_MODE14)	/*	0x2D4	*/
		MCASP1_AXR9	(PIN_INPUT | MUX_MODE14)	/*	0x2D8	*/
		MCASP1_AXR10	(PIN_INPUT | MUX_MODE14)	/*	0x2DC	*/
		MCASP1_AXR11	(PIN_INPUT | MUX_MODE14)	/*	0x2E0	*/
		MCASP1_AXR12	(PIN_INPUT | MUX_MODE14)	/*	0x2E4	*/
		MCASP1_AXR13	(PIN_INPUT | MUX_MODE14)	/*	0x2E8	*/
		MCASP1_AXR14	(PIN_INPUT | MUX_MODE14)	/*	0x2EC	*/
		MCASP1_AXR15	(PIN_INPUT | MUX_MODE14)	/*	0x2F0	*/
		MCASP2_AXR2	(PIN_INPUT | MUX_MODE14)	/*	0x30C	*/
		MCASP2_AXR3	(PIN_INPUT | MUX_MODE14)	/*	0x310	*/
		MCASP2_AXR4	(PIN_INPUT | MUX_MODE14)	/*	0x314	*/
		MCASP2_AXR5	(PIN_INPUT | MUX_MODE14)	/*	0x318	*/
		MCASP2_AXR6	(PIN_INPUT | MUX_MODE14)	/*	0x31C	*/
		MCASP2_AXR7	(PIN_INPUT | MUX_MODE14)	/*	0x320	*/
		MCASP3_ACLKX	(PIN_INPUT | MUX_MODE14)	/*	0x324	*/
		MCASP3_FSX	(PIN_INPUT | MUX_MODE14)	/*	0x328	*/
		//MMC1_CLK	(PIN_INPUT | MUX_MODE14)	/*	0x354	*/
		//MMC1_CMD	(PIN_INPUT | MUX_MODE14)	/*	0x358	*/
		//MMC1_DAT0	(PIN_INPUT | MUX_MODE14)	/*	0x35C	*/
		//MMC1_DAT1	(PIN_INPUT | MUX_MODE14)	/*	0x360	*/
		//MMC1_DAT2	(PIN_INPUT | MUX_MODE14)	/*	0x364	*/
		//MMC1_DAT3	(PIN_INPUT | MUX_MODE14)	/*	0x368	*/
		//MMC1_SDCD	(PIN_INPUT | MUX_MODE14)	/*	0x36C	*/
		//MMC1_SDWP	(PIN_INPUT | MUX_MODE14)	/*	0x370	*/
		GPIO6_10	(PIN_INPUT | MUX_MODE14)	/*	0x374	*/
		GPIO6_11	(PIN_INPUT | MUX_MODE14)	/*	0x378	*/
		MMC3_CLK	(PIN_INPUT | MUX_MODE14)	/*	0x37C	*/
		MMC3_CMD	(PIN_INPUT | MUX_MODE14)	/*	0x380	*/
		MMC3_DAT0	(PIN_INPUT | MUX_MODE14)	/*	0x384	*/
		MMC3_DAT1	(PIN_INPUT | MUX_MODE14)	/*	0x388	*/
		MMC3_DAT2	(PIN_INPUT | MUX_MODE14)	/*	0x38C	*/
		MMC3_DAT3	(PIN_INPUT | MUX_MODE14)	/*	0x390	*/
		MMC3_DAT4	(PIN_INPUT | MUX_MODE14)	/*	0x394	*/
		MMC3_DAT5	(PIN_INPUT | MUX_MODE14)	/*	0x398	*/
		MMC3_DAT6	(PIN_INPUT | MUX_MODE14)	/*	0x39C	*/
		MMC3_DAT7	(PIN_INPUT | MUX_MODE14)	/*	0x3A0	*/
		//SPI1_SCLK	(PIN_INPUT | MUX_MODE14)	/*	0x3A4	*/
		//SPI1_D1	(PIN_INPUT | MUX_MODE14)	/*	0x3A8	*/
		//SPI1_D0	(PIN_INPUT | MUX_MODE14)	/*	0x3AC	*/
		//SPI1_CS0	(PIN_INPUT | MUX_MODE14)	/*	0x3B0	*/
		//SPI1_CS1	(PIN_INPUT | MUX_MODE14)	/*	0x3B4	*/
		SPI1_CS2	(PIN_INPUT | MUX_MODE14)	/*	0x3B8	*/
		//SPI1_CS3	(PIN_INPUT | MUX_MODE14)	/*	0x3BC	*/
		//SPI2_SCLK	(PIN_INPUT | MUX_MODE14)	/*	0x3C0	*/
		//SPI2_D1	(PIN_INPUT | MUX_MODE14)	/*	0x3C4	*/
		//SPI2_D0	(PIN_INPUT | MUX_MODE14)	/*	0x3C8	*/
		//SPI2_CS0	(PIN_INPUT | MUX_MODE14)	/*	0x3CC	*/
		DCAN1_TX	(PIN_INPUT | MUX_MODE14)	/*	0x3D0	*/
		DCAN1_RX	(PIN_INPUT | MUX_MODE14)	/*	0x3D4	*/
		DCAN2_TX	(PIN_INPUT | MUX_MODE14)	/*	0x3D8	*/
		DCAN2_RX	(PIN_INPUT | MUX_MODE14)	/*	0x3DC	*/
		UART1_RXD	(PIN_INPUT | MUX_MODE14)	/*	0x3E0	*/
		UART1_TXD	(PIN_INPUT | MUX_MODE14)	/*	0x3E4	*/
		//UART1_CTSN	(PIN_INPUT | MUX_MODE14)	/*	0x3E8	*/
		//UART1_RTSN	(PIN_INPUT | MUX_MODE14)	/*	0x3EC	*/
		//UART2_RXD	(PIN_INPUT | MUX_MODE14)	/*	0x3F0	*/
		//UART2_TXD	(PIN_INPUT | MUX_MODE14)	/*	0x3F4	*/
		//UART2_CTSN	(PIN_INPUT | MUX_MODE14)	/*	0x3F8	*/
		//UART2_RTSN	(PIN_INPUT | MUX_MODE14)	/*	0x3FC	*/
		WAKEUP0	(PIN_INPUT | MUX_MODE14)	/*	0x418	*/
		WAKEUP1	(PIN_INPUT | MUX_MODE14)	/*	0x41C	*/
		WAKEUP2	(PIN_INPUT | MUX_MODE14)	/*	0x420	*/
		WAKEUP3	(PIN_INPUT | MUX_MODE14)	/*	0x424	*/
		TDI	(PIN_INPUT | MUX_MODE14)	/*	0x434	*/
		TDO	(PIN_INPUT | MUX_MODE14)	/*	0x438	*/
		TCLK	(PIN_INPUT | MUX_MODE14)	/*	0x43C	*/
		TRSTN	(PIN_INPUT | MUX_MODE14)	/*	0x440	*/
		RTCK	(PIN_INPUT | MUX_MODE14)	/*	0x444	*/
		EMU2	(PIN_INPUT | MUX_MODE14)	/*	0x450	*/
		EMU3	(PIN_INPUT | MUX_MODE14)	/*	0x454	*/

//===================================================================================
			
		>;
	};


	hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
		pinctrl-single,pins = <
			/* this pin is used as a GPIO via mcasp */
			0x2fc	(PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
		>;
	};

	hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
		pinctrl-single,pins = <
			0x408	(PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
			0x40c	(PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
		>;
	};

	hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
		pinctrl-single,pins = <
			0x408	(PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
			0x40c	(PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
		>;
	};

	dcan1_pins_default: dcan1_pins_default {
		pinctrl-single,pins = <
			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* dcan1_tx */
			0x418   (PULL_UP | MUX_MODE1)		/* wakeup0.dcan1_rx */
		>;
	};

	dcan1_pins_sleep: dcan1_pins_sleep {
		pinctrl-single,pins = <
			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
		>;
	};

	mmc1_pins_default: pinmux_mmc1_default_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
			//0x36c (PIN_INPUT | MUX_MODE14)		/* mmc1sdcd.gpio187 */
		>;
	};

	mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_hs: pinmux_mmc1_hs_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc2_pins_default: mmc2_pins_default {
		pinctrl-single,pins = <
			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs: pinmux_mmc2_hs_pins {
		pinctrl-single,pins = <
			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_ddr_3_3v: pinmux_mmc2_ddr_3_3v_pins {
		pinctrl-single,pins = <
			0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};
	
	mmc4_pins_default: pinmux_mmc4_default_pins {
		pinctrl-single,pins = <
			UART1_CTSN (PIN_INPUT_PULLUP | MUX_MODE3)	/* mmc1_clk.clk */
			UART1_RTSN (PIN_INPUT_PULLUP | MUX_MODE3)	/* mmc1_cmd.cmd */
			UART2_RXD  (PIN_INPUT_PULLUP | MUX_MODE3)	/* mmc1_dat0.dat0 */
			UART2_TXD  (PIN_INPUT_PULLUP | MUX_MODE3)	/* mmc1_dat1.dat1 */
			UART2_CTSN (PIN_INPUT_PULLUP | MUX_MODE3)	/* mmc1_dat2.dat2 */
			UART2_RTSN (PIN_INPUT_PULLUP | MUX_MODE3)	/* mmc1_dat3.dat3 */
		>;
	};	
	
	uart3_pins_default: pinmux_uart3_pins {
		pinctrl-single,pins = <
			0x34c (PIN_INPUT | MUX_MODE4) /* mcasp5_axr0.uart3_rxd */
			0x350 (PIN_OUTPUT | MUX_MODE4) /* mcasp5_axr1.uart3_txd */
		>;
	};

	uart5_pins_default: pinmux_uart5_pins {
		pinctrl-single,pins = <
			VOUT1_D0 (WAKEUP_EN | PIN_INPUT | MUX_MODE2)	/* vout1_d0.uart5_rxd */
			VOUT1_D1 (PIN_OUTPUT | MUX_MODE2)						/* vout1_d1.uart5_txd */
		>;
	};
	
	uart6_pins_default: pinmux_uart6_pins {
		pinctrl-single,pins = <
			VOUT1_D8 (PIN_INPUT | MUX_MODE2)  /* vout1_d8.uart6_rxd */
			VOUT1_D9 (PIN_OUTPUT | MUX_MODE2) /* vout1_d9.uart6_txd */
			VIN2A_D4 (PIN_OUTPUT | MUX_MODE8)  /* vin2a_d4.uart6_ctsn */
			VIN2A_D5 (PIN_INPUT | MUX_MODE8) /* vin2a_d5.uart6_rtsn */				
		>;
	};
	
	uart10_pins_default: pinmux_uart10_pins {
		pinctrl-single,pins = <
			VIN2A_D2 (PIN_INPUT | MUX_MODE8)  /* vin2a_d2.uart10_rxd */
			VIN2A_D3 (PIN_OUTPUT | MUX_MODE8) /* vin2a_d3.uart10_txd */						
		>;
	};		
	
//	i2c1_pins_default: pinmux_i2c1_pins {
//		pinctrl-single,pins = <
//			I2C1_SDA (PIN_OUTPUT_PULLUP | MUX_MODE0)  /* i2c1_sda.i2c1_sda */
//			I2C1_SCL (PIN_OUTPUT_PULLUP | MUX_MODE0)  /* i2c1_scl.i2c1_scl */
//		>;
//	};			
	
//	i2c3_pins_default: pinmux_i2c3_pins {
//		pinctrl-single,pins = <
//			GPMC_ADVN_ALE (PIN_OUTPUT_PULLUP | MUX_MODE8)  /* gpmc_advn_ale.i2c3_sda -> 8 */
//			GPMC_CLK      (PIN_OUTPUT_PULLUP | MUX_MODE8)  /* gpmc_clk.i2c3_scl -> 8 */
//		>;
//	};		
	
//	i2c4_pins_default: pinmux_i2c4_pins {
//		pinctrl-single,pins = <
//			MMC1_SDCD (PIN_OUTPUT_PULLUP | MUX_MODE4)  /* mmc1_sdcd.i2c4_sda -> 4 */
//			MMC1_SDWP (PIN_OUTPUT_PULLUP | MUX_MODE4)  /* mmc1_sdwp.i2c4_scl -> 4 */
//		>;
//	};	
		
//	i2c5_pins_default: pinmux_i2c5_pins {
//		pinctrl-single,pins = <
//			MCASP1_AXR0 (PIN_OUTPUT_PULLUP | MUX_MODE10)  /* mcasp1_axr0.i2c5_sda -> 10 */
//			MCASP1_AXR1 (PIN_OUTPUT_PULLUP | MUX_MODE10)  /* mcasp1_axr1.i2c5_scl -> 10 */
//		>;							
//	};	

};

&dra7_iodelay_core {
	mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
		pinctrl-single,pins = <
			0x618 (A_DELAY(572) | G_DELAY(540))	/* CFG_MMC1_CLK_IN */
			0x624 (A_DELAY(0) | G_DELAY(600))	/* CFG_MMC1_CMD_IN */
			0x630 (A_DELAY(403) | G_DELAY(120))	/* CFG_MMC1_DAT0_IN */
			0x63c (A_DELAY(23) | G_DELAY(60))	/* CFG_MMC1_DAT1_IN */
			0x648 (A_DELAY(25) | G_DELAY(60))	/* CFG_MMC1_DAT2_IN */
			0x654 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_IN */
			0x620 (A_DELAY(1525) | G_DELAY(0))	/* CFG_MMC1_CLK_IN */
			0x628 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OEN */
			0x62c (A_DELAY(55) | G_DELAY(0))	/* CFG_MMC1_CMD_OUT */
			0x634 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OEN */
			0x638 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OUT */
			0x640 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OEN */
			0x644 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OUT */
			0x64c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OEN */
			0x650 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OUT */
			0x658 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OEN */
			0x65c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OUT */
		>;
	};

	mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf {
		pinctrl-single,pins = <
			0x18c (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A19_IN */
			0x1a4 (A_DELAY(265) | G_DELAY(360))	/* CFG_GPMC_A20_IN */
			0x1b0 (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A21_IN */
			0x1bc (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A22_IN */
			0x1c8 (A_DELAY(287) | G_DELAY(420))	/* CFG_GPMC_A23_IN */
			0x1d4 (A_DELAY(144) | G_DELAY(240))	/* CFG_GPMC_A24_IN */
			0x1e0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_IN */
			0x1ec (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A26_IN */
			0x1f8 (A_DELAY(120) | G_DELAY(180))	/* CFG_GPMC_A27_IN */
			0x360 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_IN */
			0x190 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A19_OEN */
			0x194 (A_DELAY(174) | G_DELAY(0))	/* CFG_GPMC_A19_OUT */
			0x1a8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A20_OEN */
			0x1ac (A_DELAY(168) | G_DELAY(0))	/* CFG_GPMC_A20_OUT */
			0x1b4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A21_OEN */
			0x1b8 (A_DELAY(136) | G_DELAY(0))	/* CFG_GPMC_A21_OUT */
			0x1c0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OEN */
			0x1c4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OUT */
			0x1d0 (A_DELAY(879) | G_DELAY(0))	/* CFG_GPMC_A23_OUT */
			0x1d8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OEN */
			0x1dc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OUT */
			0x1e4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_OEN */
			0x1e8 (A_DELAY(34) | G_DELAY(0))	/* CFG_GPMC_A25_OUT */
			0x1f0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A26_OEN */
			0x1f4 (A_DELAY(120) | G_DELAY(0))	/* CFG_GPMC_A26_OUT */
			0x1fc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OEN */
			0x200 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OUT */
			0x364 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_OEN */
			0x368 (A_DELAY(11) | G_DELAY(0))	/* CFG_GPMC_CS1_OUT */
		>;
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	tps659038: tps659038@58 {
		compatible = "ti,tps659038";
		reg = <0x58>;

		tps659038_pmic {
			compatible = "ti,tps659038-pmic";

			regulators {
				smps123_reg: smps123 {
					/* VDD_MPU */
					regulator-name = "smps123";
					regulator-min-microvolt = < 850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps45_reg: smps45 {
					/* VDD_DSPEVE */
					regulator-name = "smps45";
					regulator-min-microvolt = < 850000>;
					regulator-max-microvolt = <1150000>;
					regulator-boot-on;
					regulator-always-on;
				};

				smps6_reg: smps6 {
					/* VDD_GPU - over VDD_SMPS6 */
					regulator-name = "smps6";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1250000>;
					regulator-boot-on;
					regulator-always-on;
				};

				smps7_reg: smps7 {
					/* CORE_VDD */
					regulator-name = "smps7";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1060000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps8_reg: smps8 {
					/* VDD_IVAHD */
					regulator-name = "smps8";
					regulator-min-microvolt = < 850000>;
					regulator-max-microvolt = <1250000>;
					regulator-boot-on;
					regulator-always-on;
				};

				smps9_reg: smps9 {
					/* VDDS1V8 */
					regulator-name = "smps9";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo1_reg: ldo1 {
					/* LDO1_OUT --> SDIO  */
					regulator-name = "ldo1";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
					regulator-always-on;
				};

				ldo2_reg: ldo2 {
					/* VDD_RTCIO */
					/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
					regulator-name = "ldo2";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
					regulator-always-on;
				};

				ldo3_reg: ldo3 {
					/* VDDA_1V8_PHY */
					regulator-name = "ldo3";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo9_reg: ldo9 {
					/* VDD_RTC */
					regulator-name = "ldo9";
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
					regulator-boot-on;
					regulator-always-on;
				};

				ldoln_reg: ldoln {
					/* VDDA_1V8_PLL */
					regulator-name = "ldoln";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldousb_reg: ldousb {
					/* VDDA_3V_USB: VDDA_USBHS33 */
					regulator-name = "ldousb";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
					regulator-always-on;
				};

				/* REGEN1 is unused */

				regen2: regen2 {
					/* Needed for PMIC internal resources */
					regulator-name = "regen2";
					regulator-boot-on;
					regulator-always-on;
				};

				/* REGEN3 is unused */

				sysen1: sysen1 {
					/* PMIC_REGEN_3V3 */
					regulator-name = "sysen1";
					regulator-boot-on;
					regulator-always-on;
				};

				sysen2: sysen2 {
					/* PMIC_REGEN_DDR */
					regulator-name = "sysen2";
					regulator-boot-on;
					regulator-always-on;
				};
			};
		};
	};

	pcf_lcd: gpio@20 {
		status = "disabled";
		compatible = "nxp,pcf8575";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pcf_gpio_21: gpio@21 {
		status = "disabled";
		compatible = "nxp,pcf8575";
		reg = <0x21>;
		lines-initial-states = <0x1408>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio6>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};


	tlv320aic3106: tlv320aic3106@18 {
		compatible = "ti,tlv320aic3106";
		reg = <0x18>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;		/* 2.0V */
		//status = "okay";
		status = "disabled";

		/* Regulators */
		AVDD-supply = <&evm_3v3_sw>;
		IOVDD-supply = <&evm_3v3_sw>;
		DRVDD-supply = <&evm_3v3_sw>;
		DVDD-supply = <&aic_dvdd>;
	};
};

i2c_p3_exp: &i2c2 {
	status = "okay";
	clock-frequency = <400000>;

	pcf_hdmi: gpio@26 {
		compatible = "nxp,pcf8575";
		reg = <0x26>;
		lines-initial-states = <0xffeb>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	ov10633@37 {
		compatible = "ovti,ov10633";
		reg = <0x37>;

		mux-gpios = <&pcf_hdmi 3	GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
		port {
			onboardLI: endpoint {
				//remote-endpoint = <&vin1a>;
				remote-endpoint = <&vin4b>;				
				hsync-active = <1>;
				vsync-active = <1>;
				pclk-sample = <0>;
			};
		};
	};
};

&i2c3 {
	status = "okay";
	clock-frequency = <400000>;
//	pinctrl-names = "default";
//	pinctrl-0 = <&i2c3_pins_default>;	
};

&i2c4 {
	status = "okay";
	clock-frequency = <400000>;
//	pinctrl-names = "default";
//	pinctrl-0 = <&i2c4_pins_default>;	
};

&i2c5 {
	status = "okay";
	clock-frequency = <400000>;
//	pinctrl-names = "default";
//	pinctrl-0 = <&i2c5_pins_default>;	
};


&mcspi1 {
	status = "okay";
	ti,pindir-d0-out-d1-in;
	spidev@0
	{
    spi-max-frequency = <100000>;
    reg = <0>;
  	compatible = "rohm,dh2228fv";	
	};
	spidev@1
	{
    spi-max-frequency = <100000>;
    reg = <1>;
  	compatible = "rohm,dh2228fv";	
	};		
	spidev@3
	{
    spi-max-frequency = <100000>;
    reg = <3>;
  	compatible = "rohm,dh2228fv";	
	};	
};

&mcspi2 {
	status = "okay";
	ti,pindir-d0-out-d1-in;
	spidev@0
	{
    spi-max-frequency = <100000>;
    reg = <0>;
  	compatible = "rohm,dh2228fv";	
	};
};

&mcspi3 {
	status = "okay";
	ti,pindir-d0-out-d1-in;
	spidev@0
	{
    spi-max-frequency = <100000>;
    reg = <0>;
  	compatible = "rohm,dh2228fv";	
	};
};

&uart1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;	
		
	//interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH &dra7_pmx_core 0x3e0>;	       
};

&uart2 {
	status = "okay";
};

&uart3 {
	status = "okay";
	/* gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>; */
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_pins_default>;	
};

&uart5 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart5_pins_default>;	
};

&uart6 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart6_pins_default>;	
};

&uart10 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart10_pins_default>;	
};


&mmc1 {
	status = "okay";
	pbias-supply = <&pbias_mmc_reg>;
	vmmc-supply = <&evm_3v3_sd>;
	vmmc_aux-supply = <&ldo1_reg>;
	bus-width = <4>;
	/*
	 * SDCD signal is not being used here - using the fact that GPIO mode
	 * is always hardwired.
	 */
	/* cd-gpios = <&gpio6 27 0>;*/
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "ddr50";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
	sd-uhs-ddr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
};

&mmc2 {
	status = "okay";
	vmmc-supply = <&evm_3v3_sw>;
	bus-width = <8>;
	pinctrl-names = "default", "hs", "ddr_3_3v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>;
	mmc-ddr-1_8v;
};

&mmc4 {
	status = "okay";

	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc4_pins_default>;
/*
	status = "okay";
	vmmc-supply = <&vmmcwl_fixed>;
	bus-width = <4>;
	cap-power-off-card;
	keep-power-in-suspend;
	ti,non-removable;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@0 {
		compatible = "ti,wlcore";
		reg = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
	};
*/

};

&cpu0 {
	cpu0-voltdm = <&voltdm_mpu>;
	voltage-tolerance = <1>;
};

&voltdm_mpu {
	vdd-supply = <&smps123_reg>;
};

&voltdm_dspeve {
	vdd-supply = <&smps45_reg>;
};

&voltdm_gpu {
	vdd-supply = <&smps6_reg>;
};

&voltdm_ivahd {
	vdd-supply = <&smps8_reg>;
};

&voltdm_core {
	vdd-supply = <&smps7_reg>;
};

&qspi {
	//status = "okay";
	status = "disabled";
	spi-max-frequency = <48000000>;
	m25p80@0 {
		compatible = "s25fl256s1";
		spi-max-frequency = <48000000>;
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-cpol;
		spi-cpha;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
			label = "QSPI.SPL";
			reg = <0x00000000 0x000010000>;
		};
		partition@1 {
			label = "QSPI.SPL.backup1";
			reg = <0x00010000 0x00010000>;
		};
		partition@2 {
			label = "QSPI.SPL.backup2";
			reg = <0x00020000 0x00010000>;
		};
		partition@3 {
			label = "QSPI.SPL.backup3";
			reg = <0x00030000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.u-boot";
			reg = <0x00040000 0x00100000>;
		};
		partition@5 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00140000 0x00080000>;
		};
		partition@6 {
			label = "QSPI.u-boot-env";
			reg = <0x001c0000 0x00010000>;
		};
		partition@7 {
			label = "QSPI.u-boot-env.backup1";
			reg = <0x001d0000 0x0010000>;
		};
		partition@8 {
			label = "QSPI.kernel";
			reg = <0x001e0000 0x0800000>;
		};
		partition@9 {
			label = "QSPI.file-system";
			reg = <0x009e0000 0x01620000>;
		};
	};
};

//&omap_dwc3_1 {
//	extcon = <&extcon_usb1>;
//};

//&omap_dwc3_2 {
//	extcon = <&extcon_usb2>;
//};

&usb1 {
	status = "ok";
	dr_mode = "host";
};

&usb2 {
	status = "ok";
	dr_mode = "host";
};

&mac {
	//status = "okay";
	status = "disabled";
	dual_emac;
	ti,no-idle;
};

&cpsw_emac0 {
	status = "disabled";
	phy_id = <&davinci_mdio>, <2>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	status = "disabled";
	phy_id = <&davinci_mdio>, <3>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <2>;
};

&elm {
	status = "okay";
};

&gpmc {
	status = "disabled";
	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		reg = <0 0 4>;		/* device IO registers */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <80>;
		gpmc,cs-wr-off-ns = <80>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <60>;
		gpmc,adv-wr-off-ns = <60>;
		gpmc,we-on-ns = <10>;
		gpmc,we-off-ns = <50>;
		gpmc,oe-on-ns = <4>;
		gpmc,oe-off-ns = <40>;
		gpmc,access-ns = <40>;
		gpmc,wr-access-ns = <80>;
		gpmc,rd-cycle-ns = <80>;
		gpmc,wr-cycle-ns = <80>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x000020000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00020000 0x00020000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00040000 0x00020000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x00060000 0x00020000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00080000 0x00040000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x000c0000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x001c0000 0x00020000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x001e0000 0x00020000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00200000 0x00800000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x0f600000>;
		};
	};
};

&gpio7 {
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&dss {
	status = "ok";

	vdda_video-supply = <&ldoln_reg>;
};

&hdmi {
	status = "ok";
	vdda-supply = <&ldo3_reg>;

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&tpd12s015_in>;
		};
	};
};

&dcan1 {
	//status = "ok";
	status = "disabled";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&dcan1_pins_default>;
	pinctrl-1 = <&dcan1_pins_sleep>;
};

&mailbox5 {
	status = "okay";
	mbox_ipu1_legacy: mbox_ipu1_legacy {
		status = "okay";
	};
	mbox_dsp1_legacy: mbox_dsp1_legacy {
		status = "okay";
	};
};

&mailbox6 {
	status = "okay";
	mbox_ipu2_legacy: mbox_ipu2_legacy {
		status = "okay";
	};
	mbox_dsp2_legacy: mbox_dsp2_legacy {
		status = "okay";
	};
};

&mmu0_dsp1 {
	status = "okay";
};

&mmu1_dsp1 {
	status = "okay";
};

&mmu0_dsp2 {
	status = "okay";
};

&mmu1_dsp2 {
	status = "okay";
};

&mmu_ipu1 {
	status = "okay";
};

&mmu_ipu2 {
	status = "okay";
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_cma_pool>;
	mboxes = <&mailbox6 &mbox_ipu2_legacy>;
	timers = <&timer3>;
	watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_cma_pool>;
	mboxes = <&mailbox5 &mbox_ipu1_legacy>;
	timers = <&timer11>;
	watchdog-timers = <&timer7>, <&timer8>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
	mboxes = <&mailbox5 &mbox_dsp1_legacy>;
	timers = <&timer5>;
	watchdog-timers = <&timer10>;
};

&dsp2 {
	status = "okay";
	memory-region = <&dsp2_cma_pool>;
	mboxes = <&mailbox6 &mbox_dsp2_legacy>;
	timers = <&timer6>;
};

&atl {
	status = "okay";

	atl2 {
		bws = <DRA7_ATL_WS_MCASP2_FSX>;
		aws = <DRA7_ATL_WS_MCASP3_FSX>;
	};
};

&mcasp3 {
	fck_parent = "atl_clkin2_ck";

	status = "okay";

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializer */
	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <8>;
	rx-num-evt = <8>;
};

&mcasp7 {
	#sound-dai-cells = <0>;

	status = "okay";

	op-mode = <0>;  /* MCASP_IIS_MODE */
	tdm-slots = <4>;
	/* 4 serializer */
	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
		2 1 0 0
	>;
	tx-num-evt = <8>;
	rx-num-evt = <8>;
};

&mcasp8 {
	/* not used for audio. only the AXR2 pin is used as GPIO */
	status = "okay";
};

&usb2_phy1 {
	phy-supply = <&ldousb_reg>;
};

&usb2_phy2 {
	phy-supply = <&ldousb_reg>;
};

//&vip1 {
//	status = "okay";
//};

&vip2 {
	status = "okay";
};

//video_in: &vin1a {
video_in: &vin4b {
	status = "okay";
	endpoint@0 {
		slave-mode;
		remote-endpoint = <&onboardLI>;
	};
};

#include "dra7xx-jamr3.dtsi"
//
//&tvp_5158{
//	mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_HIGH>,	/*CAM_FPD_MUX_S0*/
//			<&pcf_jamr3_21 8 GPIO_ACTIVE_LOW>;	/*SEL_TVP_FPD*/
//};