/* * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /dts-v1/; #include "dra74x.dtsi" #include #include #include #include / { model = "TI DRA742"; compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; memory { device_type = "memory"; //reg = <0x80000000 0x60000000>; /* 1536 MB */ //reg = <0x80000000 0x80000000>; /* 2048 MB */ reg = <0x80000000 0x20000000>; /* 512 MB */ }; dsa@0 { compatible = "marvell,dsa"; #address-cells = <2>; #size-cells = <0>; interrupts = <10>; dsa,ethernet = <&mac>; dsa,mii-bus = <&davinci_mdio>; switch@0 { #address-cells = <1>; #size-cells = <0>; reg = <0 0>; /* MDIO address 0, switch 0 in tree */ port@0 { reg = <0>; label = "lan1"; phy-handle = <&davinci_mdio>; }; port@1 { reg = <1>; label = "lan2"; phy-handle = <&davinci_mdio>; }; port@2 { reg = <2>; label = "lan3"; phy-handle = <&davinci_mdio>; }; port@3 { reg = <3>; label = "lan4"; phy-handle = <&davinci_mdio>; }; /* port@4 { reg = <4>; label = "lan5"; phy-handle = <&davinci_mdio>; }; */ port@5 { reg = <5>; label = "cpu"; phy-handle = <&davinci_mdio>; }; }; }; gpio-keys { compatible = "gpio-keys"; soc_reset_out { label = "soc_reset_out"; gpios = <&gpio3 7 0>; gpio-key,wakeup; linux,code = <2>; // key }; }; leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_default>; compatible = "gpio-leds"; led@1 { label = "V1P8_N"; gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; led@2 { label = "V3P3_N"; gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; led@3 { label = "eMMC_RST"; gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@4 { label = "eMMC_PWR_EN_N"; gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; led@5 { label = "UART_MUX_1"; gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@6 { label = "UART_MUX_0"; gpios = <&gpio8 4 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; led@7 { label = "ETH_RST_N"; gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@8 { label = "LGA_SYSBOOT_1"; gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@9 { label = "LGA_SYSBOOT_2"; gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@10 { label = "LGA_SYSBOOT_3"; gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; led@11 { label = "FPGA_RST_N"; gpios = <&gpio8 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@12 { label = "WLAN_V3P3_EN_N"; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; led@13 { label = "MD_12VPA_EN"; gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@14 { label = "MD_12VPB_EN"; gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@15 { label = "eMD_V5P0_EN"; gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@16 { label = "eMD_V3P3_EN"; gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@17 { label = "SATA_PATH_EN"; gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@18 { label = "SOC_POWER_ON"; gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@19 { label = "SOC_RESET_IN"; gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@20 { label = "LGA_SYSBOOT_5"; gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; led@21 { label = "FPGA_GPIO5"; gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@22 { label = "FPGA_GPIO3"; gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@23 { label = "BOOT_MODE0"; gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@24 { label = "BOOT_MODE1"; gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; led@25 { label = "PCIE_RST"; gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@26 { label = "PCIE_EN"; gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@27 { label = "PCIECLK_RESET_N"; gpios = <&gpio8 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@28 { label = "USB_SEL"; gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; led@29 { label = "HS_OE_N"; gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; }; }; reserved_mem: reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; ipu2_cma_pool: ipu2_cma@95800000 { compatible = "shared-dma-pool"; reg = <0x95800000 0x3800000>; reusable; status = "okay"; }; dsp1_cma_pool: dsp1_cma@99000000 { compatible = "shared-dma-pool"; reg = <0x99000000 0x4000000>; reusable; status = "okay"; }; ipu1_cma_pool: ipu1_cma@9d000000 { compatible = "shared-dma-pool"; reg = <0x9d000000 0x2000000>; reusable; status = "okay"; }; dsp2_cma_pool: dsp2_cma@9f000000 { compatible = "shared-dma-pool"; reg = <0x9f000000 0x800000>; reusable; status = "okay"; }; }; /* extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; }; extcon_usb2: extcon_usb2 { compatible = "linux,extcon-usb-gpio"; id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; }; */ evm_3v3_sd: fixedregulator-evm_3v3_sd { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; evm_3v3_sw: fixedregulator-evm_3v3_sw { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sw"; vin-supply = <&sysen1>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; aic_dvdd: fixedregulator-aic_dvdd { /* TPS77018DBVT */ compatible = "regulator-fixed"; regulator-name = "aic_dvdd"; vin-supply = <&evm_3v3_sw>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; vmmcwl_fixed: fixedregulator-mmcwl { compatible = "regulator-fixed"; regulator-name = "vmmcwl_fixed"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; //gpio = <&gpio5 8 0>; /* gpio5_8 */ startup-delay-us = <70000>; //enable-active-high; }; kim { compatible = "kim"; nshutdown_gpio = <132>; dev_name = "/dev/ttyS2"; flow_cntrl = <1>; baud_rate = <3686400>; }; btwilink { compatible = "btwilink"; }; vtt_fixed: fixedregulator-vtt { compatible = "regulator-fixed"; regulator-name = "vtt_fixed"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-boot-on; //enable-active-high; vin-supply = <&sysen2>; //gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; }; aliases { display0 = &hdmi0; //sound0 = &primary_sound; //sound1 = &hdmi; }; hdmi0: connector@1 { compatible = "hdmi-connector"; label = "hdmi"; type = "a"; port { hdmi_connector_in: endpoint { remote-endpoint = <&tpd12s015_out>; }; }; }; tpd12s015: encoder@1 { compatible = "ti,dra7evm-tpd12s015"; pinctrl-names = "i2c", "ddc"; pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>; pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>; ddc-i2c-bus = <&i2c2>; mcasp-gpio = <&mcasp8>; gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */ <&pcf_hdmi 5 0>, /* P5, LS OE */ <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */ ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; tpd12s015_in: endpoint@0 { remote-endpoint = <&hdmi_out>; }; }; port@1 { reg = <1>; tpd12s015_out: endpoint@0 { remote-endpoint = <&hdmi_connector_in>; }; }; }; }; ocp { gpu: gpu@0x56000000 { gpu0-voltdm = <&voltdm_gpu>; }; }; /* primary_sound: primary_sound { compatible = "ti,dra7xx-evm-audio"; ti,model = "DRA7xx-EVM"; ti,always-on; ti,audio-codec = <&tlv320aic3106>; ti,mcasp-controller = <&mcasp3>; ti,codec-clock-rate = <11289600>; clocks = <&atl_clkin2_ck>; clock-names = "mclk"; ti,audio-routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", "Line Out", "LLOUT", "Line Out", "RLOUT", "MIC3L", "Mic Jack", "MIC3R", "Mic Jack", "Mic Jack", "Mic Bias", "LINE1L", "Line In", "LINE1R", "Line In"; }; */ btwilink_sound: btwilink_sound { #sound-dai-cells = <0>; compatible = "linux,bt-sco-audio"; status = "okay"; }; simple_bt_sco_card: bt_sco_card { compatible = "simple-audio-card"; simple-audio-card,name = "DRA7xx-WiLink"; simple-audio-card,format = "dsp_a"; simple-audio-card,frame-master = <&btwilink_codec>; simple-audio-card,bitclock-master = <&btwilink_codec>; simple-audio-card,frame-inversion; simple-audio-card,cpu { sound-dai = <&mcasp7>; }; btwilink_codec: simple-audio-card,codec { sound-dai = <&btwilink_sound>; }; }; }; &dra7_pmx_core { cpsw_default: cpsw_default { pinctrl-single,pins = < // Slave 1 0x250 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) // rgmii0_tclk.rgmii0_tclk W9 0x254 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) // rgmii0_tctl.rgmii0_tctl V9 0x258 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) // rgmii0_td3.rgmii0_td3 V7 0x25c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) // rgmii0_td2.rgmii0_td2 U7 0x260 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) // rgmii0_td1.rgmii0_td1 V6 0x264 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) // rgmii0_td0.rgmii0_td0 U6 0x268 (PIN_INPUT_PULLDOWN | MUX_MODE0) // rmii0_rclk.rmii0_rclk U5 0x26c (PIN_INPUT_PULLDOWN | MUX_MODE0) // rgmii0_rctl.rgmii0_rctl V5 0x270 (PIN_INPUT_PULLDOWN | MUX_MODE0) // rgmii0_rd3.rgmii0_rd3 V4 0x274 (PIN_INPUT_PULLDOWN | MUX_MODE0) // rgmii0_rd2.rgmii0_rd2 V3 0x278 (PIN_INPUT_PULLDOWN | MUX_MODE0) // rgmii0_rd1.rgmii0_rd1 Y2 0x27c (PIN_INPUT_PULLDOWN | MUX_MODE0) // rgmii0_rd0.rgmii0_rd0 W2 /* Slave 2 */ 0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* vin2a_d12.rgmii1_tclk D5 */ 0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* vin2a_d13.rgmii1_tctl C2 */ 0x1a0 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* vin2a_d14.rgmii1_td3 C3 */ 0x1a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* vin2a_d15.rgmii1_td2 C4 */ 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* vin2a_d16.rgmii1_td1 B2 */ 0x1ac (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* vin2a_d17.rgmii1_td0 D6 */ 0x1b0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk C5 */ 0x1b4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl A3 */ 0x1b8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 B3 */ 0x1bc (PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 B4 */ 0x1c0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 B5 */ 0x1c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 A4 */ >; }; user_leds_default: user_leds_default { pinctrl-single,pins = < 0x9c (PIN_OUTPUT_PULLDOWN | MUX_MODE14) /* gpmc_a23.gpio2_13 J7 V1P8_N */ 0xa0 (PIN_OUTPUT_PULLDOWN | MUX_MODE14) /* gpmc_a24.gpio2_14 J4 V3P3_N */ 0x10c (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vin1a_d6.gpio3_10 AG6 eMMC_RST */ 0x94 (PIN_OUTPUT_PULLDOWN | MUX_MODE14) /* gpmc_a21.gpio2_11 J5 eMMC_PWR_EN_N */ 0x1e8 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vout1_d3.gpio8_3 G11 UART_MUX_1 */ 0x1ec (PIN_OUTPUT_PULLDOWN | MUX_MODE14) /* vout1_d4.gpio8_4 E9 UART_MUX_0 */ 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE14) /* mdio_clk.gpio5_15 V1 ETH_RST_N */ 0x148 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vin1a_d21.gpio3_25 AE6 LGA_SYSBOOT_1 */ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vin1a_d22.gpio3_26 AD2 LGA_SYSBOOT_2 */ 0x284 (PIN_OUTPUT_PULLDOWN | MUX_MODE14) /* usb2_drvvbus.gpio6_13 AC10 LGA_SYSBOOT_3 */ 0x200 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vout1_d9.gpio8_9 D9 FPGA_RST_N */ 0x3d4 (PIN_OUTPUT_PULLDOWN | MUX_MODE14) /* dcan1_rx.gpio1_15 G19 WLAN_V3P3_EN_N */ 0x68 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* gpmc_a10.gpio2_0 N9 MD_12VPA_EN */ 0x6c (PIN_OUTPUT_PULLUP | MUX_MODE14) /* gpmc_a11.gpio2_1 P9 MD_12VPB_EN */ 0x168 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vin2a_d0.gpio4_1 F2 eMD_V5P0_EN */ 0x16c (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vin2a_d1.gpio4_2 F3 eMD_V3P3_EN */ 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* gpmc_a6.gpio1_28 R5 SATA_PATH_EN */ 0x70 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* gpmc_a12.gpio2_2 P4 SOC_POWER_ON */ 0xfc (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vina_d2.gpio3_6 AG7 SOC_RESET_IN */ 0xa4 (PIN_OUTPUT_PULLDOWN | MUX_MODE14) /* gpmc_a25.gpio2_15 J6 LGA_SYSBOOT_5 */ 0x158 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vin2a_de0.gpio3_29 G2 FPGA_GPIO5 */ 0x188 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vin2a_d8.gpio4_9 F5 FPGA_GPIO3 */ 0x388 (PIN_OUTPUT_PULLUP | MUX_MODE14) /*mmc3_dat1.gpio7_0 AC6 BOOT_MODE0*/ 0x38c (PIN_OUTPUT_PULLDOWN | MUX_MODE14) /*mmc3_dat2.gpio7_1 AC9 BOOT_MODE1*/ 0xa8 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* gpmc_a26.gpio2_16 H4 PCIE_RST*/ 0x240 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* mdio_d.gpio5_16 U4 PCIE_EN*/ 0x1e4 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vout1_d2.gpio8_2 F10 PCIECLK_RESET_N*/ 0x140 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vin1a_d19.gpio3_23 AE1 USB_SEL */ 0x144 (PIN_OUTPUT_PULLUP | MUX_MODE14) /* vin1a_d20.gpio3_24 AE2 HS_OE_N */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < 0x190 (PIN_OUTPUT_PULLUP | MUX_MODE3) // vin2a_d10.mdio_mclk GPIO4_11 D3 0x194 (PIN_INPUT_PULLUP | MUX_MODE3) // vin2a_d11.mdio_d GPIO4_12 F6 >; }; /* davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < // MDIO //0x194 (PIN_OUTPUT_PULLUP | MUX_MODE3) // vin2a_d11.mdio_d GPIO4_12 F6 //0x190 (PIN_INPUT_PULLUP | MUX_MODE3) // vin2a_d10.mdio_mclk GPIO4_11 D3 0x198 (PIN_OUTPUT_PULLUP | MUX_MODE3) // vin2a_d12.mdio_d GPIO4_13 D5 0x19c (PIN_INPUT_PULLUP | MUX_MODE3) // vin2a_d13.mdio_mclk GPIO4_14 C2 //0x60 (PIN_OUTPUT_PULLUP | MUX_MODE0) // gpmc_a8 GPIO1_30 N7 //0x64 (PIN_OUTPUT_PULLUP | MUX_MODE0) // gpmc_a9 GPIO1_31 R4 >; }; */ uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < 0x3e0 (PIN_INPUT_PULLUP | PIN_INPUT | MUX_MODE0) /* uart1_rxd.uart1_rxd B27 */ 0x3e4 (PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd C26 */ 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn E25 */ 0x3ec (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn C27 */ >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < 0x3f0 (PIN_INPUT_PULLUP | PIN_INPUT | MUX_MODE0) /* uart2_rxd.uart2_rxd D28 */ 0x3f4 (PIN_OUTPUT | MUX_MODE0) /* uart2_txd.uart2_txd D26 */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < 0x3f8 (WAKEUP_EN | PIN_INPUT | MUX_MODE2) /* uart2_ctsn.uart3_rxd */ 0x3fc (PIN_OUTPUT | MUX_MODE1) /* uart2_rtsn.uart3_txd */ >; }; // LGA board // uart3_pins: pinmux_uart3_pins { // pinctrl-single,pins = < // 0x34c (PIN_INPUT_PULLUP | PIN_INPUT | MUX_MODE4) /* mcasp5_axr0.uart3_rxd */ // 0x350 (PIN_OUTPUT | MUX_MODE4) /* mcasp5_axr1.uart3_txd */ // >; // }; uart5_pins: pinmux_uart5_pins { pinctrl-single,pins = < 0x1dc (PIN_INPUT_PULLUP | PIN_INPUT | MUX_MODE2) /* vout1_d0.uart5_rxd F11 */ 0x1e0 (PIN_OUTPUT | MUX_MODE2) /* vout1_d1.uart5_txd G10 */ >; }; uart7_pins: pinmux_uart7_pins { pinctrl-single,pins = < 0x220 (PIN_INPUT_PULLUP | PIN_INPUT | MUX_MODE2) /* vout1_d17.uart7_rxd B8 */ 0x21c (PIN_OUTPUT | MUX_MODE2) /* vout1_d16.uart7_txd B7 */ >; }; hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin { pinctrl-single,pins = < /* this pin is used as a GPIO via mcasp */ 0x2fc (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */ >; }; hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default { pinctrl-single,pins = < 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ >; }; hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc { pinctrl-single,pins = < 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ >; }; dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ >; }; dcan1_pins_sleep: dcan1_pins_sleep { pinctrl-single,pins = < 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ >; }; mmc1_pins_default: pinmux_mmc1_default_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio187 */ >; }; mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_hs: pinmux_mmc1_hs_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; }; &dra7_iodelay_core { mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { pinctrl-single,pins = < 0x618 (A_DELAY(572) | G_DELAY(540)) /* CFG_MMC1_CLK_IN */ 0x624 (A_DELAY(0) | G_DELAY(600)) /* CFG_MMC1_CMD_IN */ 0x630 (A_DELAY(403) | G_DELAY(120)) /* CFG_MMC1_DAT0_IN */ 0x63c (A_DELAY(23) | G_DELAY(60)) /* CFG_MMC1_DAT1_IN */ 0x648 (A_DELAY(25) | G_DELAY(60)) /* CFG_MMC1_DAT2_IN */ 0x654 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */ 0x620 (A_DELAY(1525) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */ 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ 0x62c (A_DELAY(55) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ 0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ >; }; mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf { pinctrl-single,pins = < 0x18c (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A19_IN */ 0x1a4 (A_DELAY(265) | G_DELAY(360)) /* CFG_GPMC_A20_IN */ 0x1b0 (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A21_IN */ 0x1bc (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A22_IN */ 0x1c8 (A_DELAY(287) | G_DELAY(420)) /* CFG_GPMC_A23_IN */ 0x1d4 (A_DELAY(144) | G_DELAY(240)) /* CFG_GPMC_A24_IN */ 0x1e0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */ 0x1ec (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A26_IN */ 0x1f8 (A_DELAY(120) | G_DELAY(180)) /* CFG_GPMC_A27_IN */ 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */ 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ 0x194 (A_DELAY(174) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */ 0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ 0x1ac (A_DELAY(168) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ 0x1b4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ 0x1b8 (A_DELAY(136) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ 0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ 0x1c4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ 0x1d0 (A_DELAY(879) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */ 0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ 0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ 0x1e8 (A_DELAY(34) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ 0x1f0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ 0x1f4 (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ 0x1fc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ 0x368 (A_DELAY(11) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ >; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; tps659038: tps659038@58 { compatible = "ti,tps659038"; reg = <0x58>; tps659038_pmic { compatible = "ti,tps659038-pmic"; regulators { // OTP 82 /* smps123_reg: smps123 { // VDD_MPU regulator-name = "smps123"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; */ // OTP60 smps12_reg: smps12 { // VDD_MPU regulator-name = "smps12"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps3_reg: smps3 { // VDD_DDR regulator-name = "smps3"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-boot-on; regulator-always-on; }; smps45_reg: smps45 { /* VDD_DSPEVE */ regulator-name = "smps45"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; smps6_reg: smps6 { /* VDD_GPU - over VDD_SMPS6 */ regulator-name = "smps6"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-boot-on; regulator-always-on; }; smps7_reg: smps7 { /* CORE_VDD */ regulator-name = "smps7"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1060000>; regulator-always-on; regulator-boot-on; }; smps8_reg: smps8 { /* VDD_IVAHD */ regulator-name = "smps8"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1250000>; regulator-boot-on; regulator-always-on; }; smps9_reg: smps9 { /* VDDS1V8 */ regulator-name = "smps9"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldo1_reg: ldo1 { /* LDO1_OUT --> SDIO */ regulator-name = "ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo2_reg: ldo2 { /* VDD_RTCIO */ /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ regulator-name = "ldo2"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo3_reg: ldo3 { /* VDDA_1V8_PHY */ regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldo9_reg: ldo9 { /* VDD_RTC */ regulator-name = "ldo9"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-boot-on; regulator-always-on; }; ldoln_reg: ldoln { /* VDDA_1V8_PLL */ regulator-name = "ldoln"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldousb_reg: ldousb { /* VDDA_3V_USB: VDDA_USBHS33 */ regulator-name = "ldousb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; /* REGEN1 is unused */ // OTP60 regen1: regen1 { // Needed for PMIC internal resources regulator-name = "regen1"; regulator-boot-on; regulator-always-on; }; regen2: regen2 { /* Needed for PMIC internal resources */ regulator-name = "regen2"; regulator-boot-on; regulator-always-on; }; /* REGEN3 is unused */ sysen1: sysen1 { /* PMIC_REGEN_3V3 */ // GPIO4 , reference SYSEN1 register in reg map , p111 regulator-name = "sysen1"; regulator-boot-on; regulator-always-on; }; sysen2: sysen2 { /* PMIC_REGEN_DDR */ // GPIO6 regulator-name = "sysen2"; regulator-boot-on; regulator-always-on; }; }; }; }; pcf_lcd: gpio@20 { compatible = "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; }; pcf_gpio_21: gpio@21 { compatible = "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&gpio6>; interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; }; /* tlv320aic3106: tlv320aic3106@18 { compatible = "ti,tlv320aic3106"; reg = <0x18>; adc-settle-ms = <40>; ai3x-micbias-vg = <1>; // 2.0V status = "okay"; // Regulators AVDD-supply = <&evm_3v3_sw>; IOVDD-supply = <&evm_3v3_sw>; DRVDD-supply = <&evm_3v3_sw>; DVDD-supply = <&aic_dvdd>; }; */ }; i2c_p3_exp: &i2c2 { status = "okay"; clock-frequency = <400000>; pcf_hdmi: gpio@26 { compatible = "nxp,pcf8575"; reg = <0x26>; lines-initial-states = <0xffeb>; gpio-controller; #gpio-cells = <2>; }; ov10633@37 { compatible = "ovti,ov10633"; reg = <0x37>; mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */ port { onboardLI: endpoint { remote-endpoint = <&vin1a>; hsync-active = <1>; vsync-active = <1>; pclk-sample = <0>; }; }; }; }; &i2c3 { status = "okay"; clock-frequency = <3400000>; }; &mcspi1 { status = "okay"; }; &mcspi2 { status = "okay"; }; /* &uart1 { * status = "okay"; * interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH * &dra7_pmx_core 0x3e0>; * }; */ &uart1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; }; &uart2 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; }; /* * &uart3 { * status = "okay"; * gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>; * }; */ &uart3 { status = "okay"; //gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; &uart5 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart5_pins>; }; &uart7 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart7_pins>; }; &mmc1 { status = "okay"; pbias-supply = <&pbias_mmc_reg>; vmmc-supply = <&evm_3v3_sd>; vmmc_aux-supply = <&ldo1_reg>; bus-width = <4>; /* * SDCD signal is not being used here - using the fact that GPIO mode * is always hardwired. */ /* cd-gpios = <&gpio6 27 0>; */ ti,non-removable; pinctrl-names = "default", "hs", "sdr12", "sdr25", "ddr50"; pinctrl-0 = <&mmc1_pins_default>; pinctrl-1 = <&mmc1_pins_hs>; pinctrl-2 = <&mmc1_pins_sdr12>; pinctrl-3 = <&mmc1_pins_sdr25>; pinctrl-4 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>; sd-uhs-ddr50; sd-uhs-sdr25; sd-uhs-sdr12; }; // remove mmc declaration /* &mmc2 { status = "okay"; vmmc-supply = <&evm_3v3_sw>; bus-width = <8>; pinctrl-names = "default", "hs", "ddr_3_3v"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>; mmc-ddr-1_8v; }; &mmc4 { status = "okay"; vmmc-supply = <&vmmcwl_fixed>; bus-width = <4>; cap-power-off-card; keep-power-in-suspend; ti,non-removable; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@0 { compatible = "ti,wlcore"; reg = <2>; interrupt-parent = <&gpio5>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; }; }; */ &cpu0 { cpu0-voltdm = <&voltdm_mpu>; voltage-tolerance = <1>; }; &voltdm_mpu { // OTP 82 //vdd-supply = <&smps123_reg>; // OTP60 vdd-supply = <&smps12_reg>; }; &voltdm_dspeve { vdd-supply = <&smps45_reg>; }; &voltdm_gpu { vdd-supply = <&smps6_reg>; }; &voltdm_ivahd { vdd-supply = <&smps8_reg>; }; &voltdm_core { vdd-supply = <&smps7_reg>; }; &qspi { status = "okay"; spi-max-frequency = <48000000>; m25p80@0 { compatible = "s25fl256s1"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-cpol; spi-cpha; #address-cells = <1>; #size-cells = <1>; /* MTD partition table. * The ROM checks the first four physical blocks * for a valid file to boot and the flash here is * 64KiB block size. */ partition@0 { label = "QSPI.SPL"; reg = <0x00000000 0x000010000>; }; partition@1 { label = "QSPI.SPL.backup1"; reg = <0x00010000 0x00010000>; }; partition@2 { label = "QSPI.SPL.backup2"; reg = <0x00020000 0x00010000>; }; partition@3 { label = "QSPI.SPL.backup3"; reg = <0x00030000 0x00010000>; }; partition@4 { label = "QSPI.u-boot"; reg = <0x00040000 0x00100000>; }; partition@5 { label = "QSPI.u-boot-spl-os"; reg = <0x00140000 0x00080000>; }; partition@6 { label = "QSPI.u-boot-env"; reg = <0x001c0000 0x00010000>; }; partition@7 { label = "QSPI.u-boot-env.backup1"; reg = <0x001d0000 0x0010000>; }; partition@8 { label = "QSPI.kernel"; reg = <0x001e0000 0x0800000>; }; partition@9 { label = "QSPI.file-system"; reg = <0x009e0000 0x01620000>; }; }; }; /* &omap_dwc3_1 { extcon = <&extcon_usb1>; }; &omap_dwc3_2 { extcon = <&extcon_usb2>; }; */ &usb1 { //dr_mode = "otg"; dr_mode = "peripheral" ; }; &usb2 { //dr_mode = "otg"; dr_mode = "peripheral" ; }; &mac { pinctrl-names = "default"; pinctrl-0 = <&cpsw_default>; dual_emac; active_slave = <1>; ti,no-idle; status = "okay"; }; &cpsw_emac0 { // 88E1152 phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii"; status = "okay"; //dual_emac_res_vlan = <1>; }; &cpsw_emac1 { // 88E6165 phy_id = <&davinci_mdio>, <0x15>; phy-mode = "rgmii"; status = "okay"; //dual_emac_res_vlan = <2>; }; &davinci_mdio { pinctrl-names = "default"; pinctrl-0 = <&davinci_mdio_default>; status = "okay"; // dsa@0 { // }; }; /* * &cpsw_emac0 { * phy_id = <&davinci_mdio>, <2>; * phy-mode = "rgmii"; * dual_emac_res_vlan = <1>; * }; */ &elm { status = "okay"; }; &gpmc { status = "disabled"; ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { reg = <0 0 4>; /* device IO registers */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; gpmc,device-width = <2>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <80>; gpmc,cs-wr-off-ns = <80>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <60>; gpmc,adv-wr-off-ns = <60>; gpmc,we-on-ns = <10>; gpmc,we-off-ns = <50>; gpmc,oe-on-ns = <4>; gpmc,oe-off-ns = <40>; gpmc,access-ns = <40>; gpmc,wr-access-ns = <80>; gpmc,rd-cycle-ns = <80>; gpmc,wr-cycle-ns = <80>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wait-monitoring-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x000020000>; }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00020000 0x00020000>; }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00040000 0x00020000>; }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x00060000 0x00020000>; }; partition@4 { label = "NAND.u-boot-spl-os"; reg = <0x00080000 0x00040000>; }; partition@5 { label = "NAND.u-boot"; reg = <0x000c0000 0x00100000>; }; partition@6 { label = "NAND.u-boot-env"; reg = <0x001c0000 0x00020000>; }; partition@7 { label = "NAND.u-boot-env.backup1"; reg = <0x001e0000 0x00020000>; }; partition@8 { label = "NAND.kernel"; reg = <0x00200000 0x00800000>; }; partition@9 { label = "NAND.file-system"; reg = <0x00a00000 0x0f600000>; }; }; }; &gpio7 { ti,no-reset-on-init; ti,no-idle-on-init; }; &dss { status = "ok"; vdda_video-supply = <&ldoln_reg>; }; &hdmi { status = "ok"; vdda-supply = <&ldo3_reg>; port { hdmi_out: endpoint { remote-endpoint = <&tpd12s015_in>; }; }; }; &dcan1 { status = "ok"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&dcan1_pins_default>; pinctrl-1 = <&dcan1_pins_sleep>; }; &mailbox5 { status = "okay"; mbox_ipu1_legacy: mbox_ipu1_legacy { status = "okay"; }; mbox_dsp1_legacy: mbox_dsp1_legacy { status = "okay"; }; }; &mailbox6 { status = "okay"; mbox_ipu2_legacy: mbox_ipu2_legacy { status = "okay"; }; mbox_dsp2_legacy: mbox_dsp2_legacy { status = "okay"; }; }; &mmu0_dsp1 { status = "okay"; }; &mmu1_dsp1 { status = "okay"; }; &mmu0_dsp2 { status = "okay"; }; &mmu1_dsp2 { status = "okay"; }; &mmu_ipu1 { status = "okay"; }; &mmu_ipu2 { status = "okay"; }; &ipu2 { status = "okay"; memory-region = <&ipu2_cma_pool>; mboxes = <&mailbox6 &mbox_ipu2_legacy>; timers = <&timer3>; watchdog-timers = <&timer4>, <&timer9>; }; &ipu1 { status = "okay"; memory-region = <&ipu1_cma_pool>; mboxes = <&mailbox5 &mbox_ipu1_legacy>; timers = <&timer11>; watchdog-timers = <&timer7>, <&timer8>; }; &dsp1 { status = "okay"; memory-region = <&dsp1_cma_pool>; mboxes = <&mailbox5 &mbox_dsp1_legacy>; timers = <&timer5>; watchdog-timers = <&timer10>; }; &dsp2 { status = "okay"; memory-region = <&dsp2_cma_pool>; mboxes = <&mailbox6 &mbox_dsp2_legacy>; timers = <&timer6>; }; &atl { status = "okay"; atl2 { bws = ; aws = ; }; }; &mcasp3 { fck_parent = "atl_clkin2_ck"; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializer */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1 2 0 0 >; tx-num-evt = <8>; rx-num-evt = <8>; }; &mcasp7 { #sound-dai-cells = <0>; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <4>; /* 4 serializer */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 2 1 0 0 >; tx-num-evt = <8>; rx-num-evt = <8>; }; &mcasp8 { /* not used for audio. only the AXR2 pin is used as GPIO */ status = "okay"; }; &usb2_phy1 { phy-supply = <&ldousb_reg>; }; &usb2_phy2 { phy-supply = <&ldousb_reg>; }; &vip1 { status = "okay"; }; video_in: &vin1a { status = "okay"; endpoint@0 { slave-mode; remote-endpoint = <&onboardLI>; }; }; #include "dra7xx-jamr3.dtsi" &tvp_5158{ mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_HIGH>, /*CAM_FPD_MUX_S0*/ <&pcf_jamr3_21 8 GPIO_ACTIVE_LOW>; /*SEL_TVP_FPD*/ };