C66xx_24: GEL Output: Global Default Setup... C66xx_24: GEL Output: JCL modifcation, TCI6638K2K GEL file Ver is 1.70000005 C66xx_24: GEL Output: Detected PLL bypass disabled: SECCTL[BYPASS] = 0x00000000 C66xx_24: GEL Output: (3a) PLLCTL = 0x00000040 C66xx_24: GEL Output: (3b) PLLCTL = 0x00000040 C66xx_24: GEL Output: (3c) Delay... C66xx_24: GEL Output: (4)PLLM[PLLM] = 0x00000017 C66xx_24: GEL Output: MAINPLLCTL0 = 0x0B000000 C66xx_24: GEL Output: (5) MAINPLLCTL0 = 0x0B000000 C66xx_24: GEL Output: (5) MAINPLLCTL1 = 0x00000040 C66xx_24: GEL Output: (6) MAINPLLCTL0 = 0x0B000000 C66xx_24: GEL Output: (7) SECCTL = 0x00090000 C66xx_24: GEL Output: (8a) Delay... C66xx_24: GEL Output: PLL1_DIV3 = 0x00008002 C66xx_24: GEL Output: PLL1_DIV4 = 0x00008004 C66xx_24: GEL Output: PLL1_DIV7 = 0x00000000 C66xx_24: GEL Output: (8d/e) Delay... C66xx_24: GEL Output: (10) Delay... C66xx_24: GEL Output: (12) Delay... C66xx_24: GEL Output: (13) SECCTL = 0x00090000 C66xx_24: GEL Output: (Delay... C66xx_24: GEL Output: (Delay... C66xx_24: GEL Output: (14) PLLCTL = 0x00000041 C66xx_24: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT): C66xx_24: GEL Output: PLL has been configured (100.0 MHz * 24 / 1 / 2 = 1200.0 MHz) C66xx_24: GEL Output: Switching on ARM Core 0 C66xx_24: GEL Output: Switching on ARM Core 1 C66xx_24: GEL Output: Switching on ARM Core 2 C66xx_24: GEL Output: Switching on ARM Core 3 C66xx_24: GEL Output: ARM PLL has been configured (100.0 MHz * 28 / 2 = 1400.0 MHz) C66xx_24: GEL Output: DISABLESTAT ---> 0x000007FF C66xx_24: GEL Output: Power on all PSC modules and DSP domains... C66xx_24: GEL Output: Power on all PSC modules and DSP domains... Done. C66xx_24: GEL Output: WARNING: ALTCORECLK is the input to the PA PLL. C66xx_24: GEL Output: Completed PA PLL Setup C66xx_24: GEL Output: PAPLLCTL0 - before: 0x0x098804C0 after: 0x0x09080500 C66xx_24: GEL Output: PAPLLCTL1 - before: 0x0x00000040 after: 0x0x00002040 C66xx_24: GEL Output: DDR begin C66xx_24: GEL Output: XMC setup complete. C66xx_24: GEL Output: DDR3 PLL Setup ... C66xx_24: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 800MHz. C66xx_24: GEL Output: DDR3 PHY Leveling Complete C66xx_24: GEL Output: DDR3A initialization complete C66xx_24: GEL Output: DDR done C66xx_24: GEL Output: Global Default Setup... Done.