/* * Copyright (c) 2010, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* * Setup platform-specific memory map: */ var mem_ext = [ { comment: "DDRALGHEAP: off-chip memory for dynamic algmem allocation", name: "DDRALGHEAP", base: 0xC3000000, len: 0x01000000, space: "code/data" }, { comment: "SDRAM: off-chip memory for application code and data", name: "SDRAM", base: 0xC2C00000, len: 0x00300000, space: "code/data" }, { comment: "DSPLINK: off-chip memory reserved for DSPLINK code and data", name: "DSPLINKMEM", base: 0xC2F01000, len: 0x00100000 - 0x1000, space: "code/data" }, { comment: "RESET_VECTOR: off-chip memory for the reset vector table", name: "RESET_VECTOR", base: 0xC2F00000, len: 0x00001000, space: "code/data" }, ]; /* * Internal memory partitioning for evmDM6446 * * On the left in the diagram below is the layout of internal memory * available on DM6446 for data caching and as RAM; on the right is the * diagram showing how this configuration file partitions the available * 64k+80k of memory. (The 32K for program cache is not affected by this * configuration.) Please find more specifics on how the configuration is * done further below. * * * Physical internal memory on DM6446 Default partitioning in this .tcf * * |//////////| |//////////| * 0x11800000 +----------+ 0x11800000 +----------+ * | L2Cache | | | * | and/or | 64k | L2 Cache | 64k * | IRAM | | | * | | | | * 0x11810000 +----------+ 0x11810000 +----------+ * |//////////| |//////////| * : : : : * |//////////| |//////////| * 0x11F04000 +----------+ 0x11F04000 +----------+ * | | | | * | L1DSRAM | 48k | L1DSRAM | * | | | | 64k * 0x11F10000 +- - - - - + | | * |L1Cache or| 32k +- - - - - + * |more L1DSR| 0x11F14000 | L1 cache | 16k * 0x11F18000 +----------+ 0x11F18000 +----------+ * |//////////| |//////////| */ /* * Configure L1D Cache and L1DSRAM segment: l1DMode * * OMAP3530 device has 48KB of physical memory at 0x10F04000 available * as internal RAM, called the "L1DSRAM" segment in BIOS, and it has * another adjacent 32KB at 0x10F10000 that can either be used entirely * for L1D cache, or split between L1D cache and more internal memory. * * The 80KB segment (48KB + 32KB) starts at 0x10F04000. When powered on, * the device uses the upper 32K for L1D cache entirely, so BIOS by default * defines the L1DSRAM segment to be 48KB long and does not change the cache. * * We can change the default behavior, by shrinking the L1D cache and adding * the extra space to L1DSRAM. We can set the L1D cache to be 32K (the default) * or 16K, 8K, 4K, or 0K. The corresponding L1DSRAM sizes then are 48K (the * default), or 64K, 72K, 76K, or 80K. * * The L1DSRAM segment always starts at 0x10F04000. * * Configure L2 Cache memory settings: l2Mode * * This value indicates how the physical internal memory of size 64KB * starting at 0x10800000 will be split between L2 cache and a * general-purpose internal memory segment IRAM. * * The options for l2Mode are: * * "0k" -- IRAM : start = 0x10800000, len = 64KB * L2 Cache: none * "32k" -- IRAM : start = 0x10800000, len = 32KB * L2 Cache: start = 0x10808000, len = 32KB * "64k" -- IRAM : none * L2 Cache: start = 0x10800000, len = 64KB */ var device_regs = { l1PMode: "32k", l1DMode: "16k", l2Mode: "128k" }; var params = { clockRate: 300, catalogName: "ti.catalog.c6000", deviceName: "L137", regs: device_regs, mem: mem_ext }; /* * Now customize the generic platform with parameters specified above. */ utils.loadPlatform("ti.platforms.generic", params); /* =========================================================================== * Enable heaps and tasks * =========================================================================== */ bios.enableMemoryHeaps(prog); bios.enableTskManager(prog); /* =========================================================================== * Create heaps in memory segments that are to have heap * =========================================================================== */ bios.SDRAM.createHeap = true; bios.SDRAM.heapSize = 0x20000; // 128K /* set for use in all.tcf */ var platformSeg = bios.SDRAM; bios.DDRALGHEAP.createHeap = true; bios.DDRALGHEAP.heapSize = bios.DDRALGHEAP.len; /* * The setting of L1DSRAM.len is to work around a problem in the BIOS 5 * bios_6747.tci file. TODO - remove when that (SDOCM00051331) is fixed. */ bios.L1DSRAM.len = 0x4000; bios.L1DSRAM.createHeap = true; bios.L1DSRAM.enableHeapLabel = true; bios.L1DSRAM["heapLabel"] = prog.extern("L1DHEAP"); bios.L1DSRAM.heapSize = bios.L1DSRAM.len; // all of L1DSRAM for this heap bios.IRAM.createHeap = true; bios.IRAM.enableHeapLabel = true; bios.IRAM["heapLabel"] = prog.extern("L2HEAP"); bios.IRAM.heapSize = 0x20000; // half of IRAM's 256K for this heap bios.L3_CBA_RAM.createHeap = true; bios.L3_CBA_RAM.enableHeapLabel = true; bios.L3_CBA_RAM["heapLabel"] = prog.extern("L3_CBA_RAM_HEAP"); bios.L3_CBA_RAM.heapSize = 0x10000; // half of L3's 128K for this heap /* =========================================================================== * GBL * =========================================================================== */ /* set MAR register to cache shared internal memory 0x80000000-0x80FFFFFF */ bios.GBL.C64PLUSMAR128to159 = 0x00000001; /* set MAR register to cache external memory 0xC0000000-0xC3FFFFFF */ bios.GBL.C64PLUSMAR192to223 = 0x0000000f; /* * @(#) ti.sdo.ce.examples.servers.all_codecs; 1, 0, 0,261; 12-2-2010 21:23:34; /db/atree/library/trees/ce/ce-r11x/src/ xlibrary */