DMSC_Cortex_M3_0: GEL Output: Configuring AM65xEVM... DMSC_Cortex_M3_0: GEL Output: Init value actual value: 0x00000888 DMSC_Cortex_M3_0: GEL Output: Register value: 0x00000888 DMSC_Cortex_M3_0: GEL Output: ATCM is on DMSC_Cortex_M3_0: GEL Output: ATCM configured. DMSC_Cortex_M3_0: GEL Output: Assuming execution from M3. DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000]. DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000]. DMSC_Cortex_M3_0: GEL Output: Setting all PLLs in progress. This may take some time. DMSC_Cortex_M3_0: GEL Output: 0 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 10 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 20 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 30 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 40 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 50 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 60 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 70 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 80 Percent Complete... DMSC_Cortex_M3_0: GEL Output: 90 Percent Complete... DMSC_Cortex_M3_0: GEL Output: Setting all PLLs done! DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress... DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP2MCU DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP2MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUG2DMSC DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_GPIO DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2WKUP DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_HYPERBUS DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_DEBUG DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_0 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_1 DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_INFRA DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CC_TOP DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_2 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_3 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_DEBUG DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CAL DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SAUL DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_COMMON DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_NB DMSC_Cortex_M3_0: GEL Output: No change needed. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_2 DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPU DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully. DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done! MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled MCU_PULSAR_Cortex_R5_0: GEL Output: PHY Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for write leveling to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000003F MCU_PULSAR_Cortex_R5_0: GEL Output: checking status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0GSR0 = 0x00892120 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1GSR0 = 0x008C21A0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2GSR0 = 0x008F23A0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3GSR0 = 0x008E22A0 MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read DQS training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read DQS training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000007F MCU_PULSAR_Cortex_R5_0: GEL Output: checking status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write leveling adjustment to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling adjustment complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800000FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800001FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800003FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800007FF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80000FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for VREF training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: VREF training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: ==== DDR4 Initialization has PASSED!!!! ==== MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled MCU_PULSAR_Cortex_R5_0: GEL Output: PHY Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for write leveling to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: checking status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0GSR0 = 0x00892120 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1GSR0 = 0x008C21A0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2GSR0 = 0x008F23A0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3GSR0 = 0x008E22A0 MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read DQS training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read DQS training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: checking status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3RSR0 = 0x00000000 MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write leveling adjustment to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling adjustment complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for VREF training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: VREF training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80004FFF MCU_PULSAR_Cortex_R5_0: GEL Output: ==== DDR4 Initialization has PASSED!!!! ====