###########################
#   Starting Bootloader   #
###########################
DrvQspi/QspiFlash Init: OK
Loaded SYSFW from 0x00180000
Board configuration:
* PinMux: OK
* PLL: OK
* Clock Manager: OK
* Power Manager: OK
* DDR Init: OK
DrvUDma Init: OK
DrvGtc Init: OK
DrvGpio Init: OK
Jacinto7 DDRSS Tools
Supported SOCs: J721E, J7200
Revision: Beta Release - September 2020 

DDRSS Instance: 0
	DRAM Type: LPDDR4
	Bus Width: 32
	Rank Count: 1

Margin Analysis Input:
	Eye Type (Select '0' for read, '1' for write): 0
	Eye Precision (VREF / DLL Step Size; impacts test time):
		VREF Step Size (enter decimal value; min value is 2): 4
		Delay Step Size (enter decimal value; min value is 8): 16
	Pattern: wc_isi_sso
	Transfer Size (bytes): 487872
eye_type=read
phy_vref_f1_bl0: 0x1f
phy_vref_f1_bl1: 0x21
phy_vref_f1_bl2: 0x20
phy_vref_f1_bl3: 0x20
read_delay_fall, f1_cs0_dq0 : 0x7e
read_delay_rise, f1_cs0_dq0 : 0x7e
read_delay_fall, f1_cs0_dq1 : 0x8a
read_delay_rise, f1_cs0_dq1 : 0x84
read_delay_fall, f1_cs0_dq2 : 0x7e
read_delay_rise, f1_cs0_dq2 : 0x84
read_delay_fall, f1_cs0_dq3 : 0x8a
read_delay_rise, f1_cs0_dq3 : 0x84
read_delay_fall, f1_cs0_dq4 : 0x84
read_delay_rise, f1_cs0_dq4 : 0x84
read_delay_fall, f1_cs0_dq5 : 0x8a
read_delay_rise, f1_cs0_dq5 : 0x84
read_delay_fall, f1_cs0_dq6 : 0x7e
read_delay_rise, f1_cs0_dq6 : 0x7e
read_delay_fall, f1_cs0_dq7 : 0x8a
read_delay_rise, f1_cs0_dq7 : 0x84
read_delay_fall, f1_cs0_dq8 : 0x90
read_delay_rise, f1_cs0_dq8 : 0x78
read_delay_fall, f1_cs0_dq9 : 0x90
read_delay_rise, f1_cs0_dq9 : 0x7e
read_delay_fall, f1_cs0_dq10 : 0x8a
read_delay_rise, f1_cs0_dq10 : 0x6c
read_delay_fall, f1_cs0_dq11 : 0x90
read_delay_rise, f1_cs0_dq11 : 0x72
read_delay_fall, f1_cs0_dq12 : 0x8a
read_delay_rise, f1_cs0_dq12 : 0x72
read_delay_fall, f1_cs0_dq13 : 0x90
read_delay_rise, f1_cs0_dq13 : 0x78
read_delay_fall, f1_cs0_dq14 : 0x90
read_delay_rise, f1_cs0_dq14 : 0x78
read_delay_fall, f1_cs0_dq15 : 0x96
read_delay_rise, f1_cs0_dq15 : 0x7e
read_delay_fall, f1_cs0_dq16 : 0x90
read_delay_rise, f1_cs0_dq16 : 0x78
read_delay_fall, f1_cs0_dq17 : 0x96
read_delay_rise, f1_cs0_dq17 : 0x7e
read_delay_fall, f1_cs0_dq18 : 0x8a
read_delay_rise, f1_cs0_dq18 : 0x78
read_delay_fall, f1_cs0_dq19 : 0x90
read_delay_rise, f1_cs0_dq19 : 0x7e
read_delay_fall, f1_cs0_dq20 : 0x8a
read_delay_rise, f1_cs0_dq20 : 0x78
read_delay_fall, f1_cs0_dq21 : 0x8a
read_delay_rise, f1_cs0_dq21 : 0x7e
read_delay_fall, f1_cs0_dq22 : 0x8a
read_delay_rise, f1_cs0_dq22 : 0x72
read_delay_fall, f1_cs0_dq23 : 0x96
read_delay_rise, f1_cs0_dq23 : 0x84
read_delay_fall, f1_cs0_dq24 : 0x7e
read_delay_rise, f1_cs0_dq24 : 0x60
read_delay_fall, f1_cs0_dq25 : 0x7e
read_delay_rise, f1_cs0_dq25 : 0x6c
read_delay_fall, f1_cs0_dq26 : 0x7e
read_delay_rise, f1_cs0_dq26 : 0x6c
read_delay_fall, f1_cs0_dq27 : 0x84
read_delay_rise, f1_cs0_dq27 : 0x6c
read_delay_fall, f1_cs0_dq28 : 0x78
read_delay_rise, f1_cs0_dq28 : 0x60
read_delay_fall, f1_cs0_dq29 : 0x84
read_delay_rise, f1_cs0_dq29 : 0x72
read_delay_fall, f1_cs0_dq30 : 0x84
read_delay_rise, f1_cs0_dq30 : 0x6c
read_delay_fall, f1_cs0_dq31 : 0x90
read_delay_rise, f1_cs0_dq31 : 0x78
phy_vref_f2_bl0: 0x20
phy_vref_f2_bl1: 0x21
phy_vref_f2_bl2: 0x20
phy_vref_f2_bl3: 0x1f
read_delay_fall, f2_cs0_dq0 : 0x7e
read_delay_rise, f2_cs0_dq0 : 0x7e
read_delay_fall, f2_cs0_dq1 : 0x8a
read_delay_rise, f2_cs0_dq1 : 0x84
read_delay_fall, f2_cs0_dq2 : 0x8a
read_delay_rise, f2_cs0_dq2 : 0x7e
read_delay_fall, f2_cs0_dq3 : 0x8a
read_delay_rise, f2_cs0_dq3 : 0x84
read_delay_fall, f2_cs0_dq4 : 0x8a
read_delay_rise, f2_cs0_dq4 : 0x84
read_delay_fall, f2_cs0_dq5 : 0x8a
read_delay_rise, f2_cs0_dq5 : 0x84
read_delay_fall, f2_cs0_dq6 : 0x84
read_delay_rise, f2_cs0_dq6 : 0x7e
read_delay_fall, f2_cs0_dq7 : 0x8a
read_delay_rise, f2_cs0_dq7 : 0x84
read_delay_fall, f2_cs0_dq8 : 0x90
read_delay_rise, f2_cs0_dq8 : 0x78
read_delay_fall, f2_cs0_dq9 : 0x90
read_delay_rise, f2_cs0_dq9 : 0x7e
read_delay_fall, f2_cs0_dq10 : 0x8a
read_delay_rise, f2_cs0_dq10 : 0x6c
read_delay_fall, f2_cs0_dq11 : 0x90
read_delay_rise, f2_cs0_dq11 : 0x78
read_delay_fall, f2_cs0_dq12 : 0x8a
read_delay_rise, f2_cs0_dq12 : 0x72
read_delay_fall, f2_cs0_dq13 : 0x90
read_delay_rise, f2_cs0_dq13 : 0x78
read_delay_fall, f2_cs0_dq14 : 0x90
read_delay_rise, f2_cs0_dq14 : 0x78
read_delay_fall, f2_cs0_dq15 : 0x96
read_delay_rise, f2_cs0_dq15 : 0x7e
read_delay_fall, f2_cs0_dq16 : 0x90
read_delay_rise, f2_cs0_dq16 : 0x78
read_delay_fall, f2_cs0_dq17 : 0x96
read_delay_rise, f2_cs0_dq17 : 0x84
read_delay_fall, f2_cs0_dq18 : 0x8a
read_delay_rise, f2_cs0_dq18 : 0x78
read_delay_fall, f2_cs0_dq19 : 0x9c
read_delay_rise, f2_cs0_dq19 : 0x7e
read_delay_fall, f2_cs0_dq20 : 0x8a
read_delay_rise, f2_cs0_dq20 : 0x78
read_delay_fall, f2_cs0_dq21 : 0x8a
read_delay_rise, f2_cs0_dq21 : 0x7e
read_delay_fall, f2_cs0_dq22 : 0x8a
read_delay_rise, f2_cs0_dq22 : 0x72
read_delay_fall, f2_cs0_dq23 : 0x96
read_delay_rise, f2_cs0_dq23 : 0x84
read_delay_fall, f2_cs0_dq24 : 0x7e
read_delay_rise, f2_cs0_dq24 : 0x60
read_delay_fall, f2_cs0_dq25 : 0x7e
read_delay_rise, f2_cs0_dq25 : 0x6c
read_delay_fall, f2_cs0_dq26 : 0x7e
read_delay_rise, f2_cs0_dq26 : 0x6c
read_delay_fall, f2_cs0_dq27 : 0x84
read_delay_rise, f2_cs0_dq27 : 0x6c
read_delay_fall, f2_cs0_dq28 : 0x78
read_delay_rise, f2_cs0_dq28 : 0x60
read_delay_fall, f2_cs0_dq29 : 0x84
read_delay_rise, f2_cs0_dq29 : 0x72
read_delay_fall, f2_cs0_dq30 : 0x84
read_delay_rise, f2_cs0_dq30 : 0x6c
read_delay_fall, f2_cs0_dq31 : 0x90
read_delay_rise, f2_cs0_dq31 : 0x78
vref=0
rddly=0