/* ======================================================================= */ /* TEXAS INSTRUMENTS, INC. */ /* */ /* FFTLIB FFT Library */ /* */ /* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ */ /* */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in the */ /* documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names of */ /* its contributors may be used to endorse or promote products derived */ /* from this software without specific prior written permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /* ======================================================================= */ #include #include #include #define EDMA_MGR_NUM_EDMA_INSTANCES 1 //3 /* In the arrays below, each bit of a 32-bit word corresponds to a single */ /* PaRAMSet/EDMAChannel/QDMAChannel/TCC owned by the corresponding region, */ /* i.e., can be used for general purpose EDMA tranfers, or reserved for */ /* EDMA transfers by hardware peripherals (cannot be used for general */ /* purpose EDMA tranfers) */ #define DMA_CHANNEL_TO_EVENT_MAPPING_0 (0x00000000u) #define DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x00000000u) /* EDMA3_InstanceInitConfig sample0 with region neither owning nor */ /* reserving any EDMA resources */ #define regionSample0 \ { \ /* Resources owned by Region */ \ /* ownPaRAMSets */ \ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \ \ /* ownDmaChannels */ \ {0xFFFFFFFFu, 0x00000000u}, \ \ /* ownQdmaChannels */ \ {0x000000FFu}, \ \ /* ownTccs */ \ {0xFFFFFFFFu, 0x00000000u}, \ \ /* Resources reserved by Region */ \ /* resvdPaRAMSets */ \ {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \ \ /* resvdDmaChannels */ \ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \ \ /* resvdQdmaChannels */ \ {0x00000000u}, \ \ /* resvdTccs */ \ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \ } /* EDMA3_InstanceInitConfig sample1 with region owning PaRAM sets 64-105, */ /* and EDMA channel 0-7, but not reserving any EDMA resources */ /* Note that the first N PaRAM sets (N=number of EDMA channels available */ /* on an EDMA instance) are reserved in EDMA3 LLD ). */ #define regionSample1 \ { \ /* Resources owned by Region */ \ /* ownPaRAMSets */ \ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, \ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \ \ /* ownDmaChannels */ \ {0x0000FFFFu, 0x00000000u}, \ \ /* ownQdmaChannels */ \ {0x00000000u}, \ \ /* ownTccs */ \ {0x0000FFFFu, 0x00000000u}, \ \ /* Resources reserved by Region */ \ /* resvdPaRAMSets */ \ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \ \ /* resvdDmaChannels */ \ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \ \ /* resvdQdmaChannels */ \ {0x00000000u}, \ \ /* resvdTccs */ \ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \ } /* EDMA3_InstanceInitConfig sample2 with region owning PaRAM sets 106-147, */ /* and EDMA channel 8-15, but not reserving any EDMA resources */ #define regionSample2 \ { \ /* Resources owned by Region */ \ /* ownPaRAMSets */ \ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \ \ /* ownDmaChannels */ \ {0xFFFF0000u, 0x00000000u}, \ \ /* ownQdmaChannels */ \ {0x00000000u}, \ \ /* ownTccs */ \ {0xFFFF0000u, 0x00000000u}, \ \ /* Resources reserved by Region */ \ /* resvdPaRAMSets */ \ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \ \ /* resvdDmaChannels */ \ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \ \ /* resvdQdmaChannels */ \ {0x00000000u}, \ \ /* resvdTccs */ \ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \ } /* EDMA3_InstanceInitConfig sample3 with region owning PaRAM sets 148-189, */ /* and EDMA channel 16-23, but not reserving any EDMA resources */ #define regionSample3 \ { \ /* Resources owned by Region */ \ /* ownPaRAMSets */ \ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \ \ /* ownDmaChannels */ \ {0x00000000u, 0x0000FFFFu}, \ \ /* ownQdmaChannels */ \ {0x00000000u}, \ \ /* ownTccs */ \ {0x00000000u, 0x0000FFFFu}, \ \ /* Resources reserved by Region */ \ /* resvdPaRAMSets */ \ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \ \ /* resvdDmaChannels */ \ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \ \ /* resvdQdmaChannels */ \ {0x00000000u}, \ \ /* resvdTccs */ \ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \ } /* EDMA3_InstanceInitConfig sample4 with region owning PaRAM sets 190-231, */ /* and EDMA channel 24-31, but not reserving any EDMA resources */ #define regionSample4 \ { \ /* Resources owned by Region */ \ /* ownPaRAMSets */ \ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu, \ 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u}, \ \ /* ownDmaChannels */ \ {0x00000000u, 0xFFFF0000u}, \ \ /* ownQdmaChannels */ \ {0x00000000u}, \ \ /* ownTccs */ \ {0x00000000u, 0xFFFF0000u}, \ \ /* Resources reserved by Region */ \ /* resvdPaRAMSets */ \ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \ \ /* resvdDmaChannels */ \ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \ \ /* resvdQdmaChannels */ \ {0x00000000u}, \ \ /* resvdTccs */ \ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \ } #define NUM_EDMA_INSTANCES 1 //3 const EDMA3_InstanceInitConfig C6678_config[NUM_EDMA_INSTANCES][EDMA3_MAX_REGIONS] = { /* EDMA3 INSTANCE# 0 */ { regionSample0, regionSample0, regionSample0, regionSample0, regionSample0, regionSample0, regionSample0, regionSample0 } /* EDMA3 INSTANCE# 1 { regionSample1, regionSample2, regionSample3, regionSample4, regionSample0, regionSample0, regionSample0, regionSample0 }, */ /* EDMA3 INSTANCE# 2 { regionSample0, regionSample0, regionSample0, regionSample0, regionSample1, regionSample2, regionSample3, regionSample4 } */ }; const EDMA3_InstanceInitConfig edmaMgrInstanceInitConfig[EDMA_MGR_NUM_EDMA_INSTANCES][EDMA3_MAX_REGIONS] = { /* EDMA3 INSTANCE# 0 */ { regionSample0, regionSample0, regionSample0, regionSample0, regionSample0, regionSample0, regionSample0, regionSample0 } /* EDMA3 INSTANCE# 1 { regionSample1, regionSample2, regionSample3, regionSample4, regionSample0, regionSample0, regionSample0, regionSample0 }, */ /* EDMA3 INSTANCE# 2 { regionSample0, regionSample0, regionSample0, regionSample0, regionSample1, regionSample2, regionSample3, regionSample4 } */ }; int32_t edmaMgrRegion2Instance[EDMA3_MAX_REGIONS] = {0,0,0,0,0,0,0,0}; //{1,1,1,1,2,2,2,2}; /* Driver Object Initialization Configuration */ EDMA3_GblConfigParams edmaMgrGblConfigParams [EDMA_MGR_NUM_EDMA_INSTANCES] = { { /* EDMA3 INSTANCE# 0 */ /** Total number of DMA Channels supported by the EDMA3 Controller */ 16u, /** Total number of QDMA Channels supported by the EDMA3 Controller */ 8u, /** Total number of TCCs supported by the EDMA3 Controller */ 16u, /** Total number of PaRAM Sets supported by the EDMA3 Controller */ 128u, /** Total number of Event Queues in the EDMA3 Controller */ 2u, /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ 2u, /** Number of Regions on this EDMA3 controller */ 8u, /** * \brief Channel mapping existence * A value of 0 (No channel mapping) implies that there is fixed association * for a channel number to a parameter entry number or, in other words, * PaRAM entry n corresponds to channel n. */ 1u, /** Existence of memory protection feature */ 1u, /** Global Register Region of CC Registers */ (void *)0x01D10000u, //0x40D10000u, //0x02700000u, /** Transfer Controller (TC) Registers */ { (void *)0x01D05000u, //0x40D05000u, //0x02760000u, (void *)0x01D06000u, //0x40D06000u, //0x02768000u, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL, (void *)NULL }, /** Interrupt no. for Transfer Completion */ 16u, //38u, /** Interrupt no. for CC Error */ 27u, //32u, /** Interrupt no. for TCs Error */ { 28u, //34u, 29u, //35u, 0u, 0u, 0u, 0u, 0u, 0u, }, /** * \brief EDMA3 TC priority setting * * User can program the priority of the Event Queues * at a system-wide level. This means that the user can set the * priority of an IO initiated by either of the TCs (Transfer Controllers) * relative to IO initiated by the other bus masters on the * device (ARM, DSP, USB, etc) */ { 0u, 1u, 0u, 0u, 0u, 0u, 0u, 0u }, /** * \brief To Configure the Threshold level of number of events * that can be queued up in the Event queues. EDMA3CC error register * (CCERR) will indicate whether or not at any instant of time the * number of events queued up in any of the event queues exceeds * or equals the threshold/watermark value that is set * in the queue watermark threshold register (QWMTHRA). */ { 16u, 16u, 0u, 0u, 0u, 0u, 0u, 0u }, /** * \brief To Configure the Default Burst Size (DBS) of TCs. * An optimally-sized command is defined by the transfer controller * default burst size (DBS). Different TCs can have different * DBS values. It is defined in Bytes. */ { 128u, 128u, 0u, 0u, 0u, 0u, 0u, 0u }, /** * \brief Mapping from each DMA channel to a Parameter RAM set, * if it exists, otherwise of no use. */ { EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, /* DMA channels 16-63 DOES NOT exist */ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS }, /** * \brief Mapping from each DMA channel to a TCC. This specific * TCC code will be returned when the transfer is completed * on the mapped channel. */ { EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, /* DMA channels 16-63 DOES NOT exist */ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC }, /** * \brief Mapping of DMA channels to Hardware Events from * various peripherals, which use EDMA for data transfer. * All channels need not be mapped, some can be free also. */ { 0x00000000u, 0x00000000u } }, }; int32_t *ti_sdo_fc_edmamgr_region2Instance = (int32_t*)&edmaMgrRegion2Instance[0]; EDMA3_GblConfigParams *ti_sdo_fc_edmamgr_edma3GblConfigParams = (EDMA3_GblConfigParams*)&edmaMgrGblConfigParams[0]; EDMA3_InstanceInitConfig *ti_sdo_fc_edmamgr_edma3RegionConfig = (EDMA3_InstanceInitConfig*)&edmaMgrInstanceInitConfig[0][0];