Cortex_R5_0: ***OnTargetConnect() Launched***

Cortex_R5_0: AM263x Initialization Scripts Launched.
Please Wait...


Cortex_R5_0: AM263x_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: Crystal Clock present
Cortex_R5_0: AM263x_SOP_Mode() Launched
Cortex_R5_0: SOP MODE = 0x0000000B    
Cortex_R5_0: Devboot mode
Cortex_R5_0: AM263x_Read_Device_Type() Launched
Cortex_R5_0: EFuse Device Type Value = 0x000000AA    
Cortex_R5_0: AM263x_Check_supported_mode() Launched
Cortex_R5_0: mode = 1

Cortex_R5_0: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: MSS_RCM Control Registers Unlocked
Cortex_R5_0: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: *** R5FSS0 DualCore Reset ***
Cortex_R5_0: *** R5FSS1 DualCore Reset ***
Cortex_R5_0: R5F ROM Eclipse
Cortex_R5_0: R5FSS0_0 Released
Cortex_R5_0: R5FSS0_1 Released
Cortex_R5_0: R5FSS1_0 Released
Cortex_R5_0: R5FSS1_1 Released
Cortex_R5_0: All R5F Cores Released for program load
Cortex_R5_0: L2 Mem Init Complete
Cortex_R5_0: MailBox Mem Init Complete
Cortex_R5_0: *********** R5FSS0/1 Dual Core mode Configured********
Cortex_R5_0: CORE PLL Configuration Complete
Cortex_R5_0: PER PLL Configuration Complete
Cortex_R5_0: SYS_CLK DIVBY2
Cortex_R5_0: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0:

 *** Enabling Peripheral Clocks ***
Cortex_R5_0: Enabling RTI[0:3] Clocks
Cortex_R5_0: RTI0 Clock Enabled (200MHz)
Cortex_R5_0: RTI1 Clock Enabled (200MHz)
Cortex_R5_0: RTI2 Clock Enabled (200MHz)
Cortex_R5_0: RTI3 Clock Enabled (200MHz)
Cortex_R5_0: Enabling RTI_WDT[0:3] Clocks
Cortex_R5_0: WDT0 Clock Enabled (200MHz)
Cortex_R5_0: WDT1 Clock Enabled (200MHz)
Cortex_R5_0: WDT2 Clock Enabled (200MHz)
Cortex_R5_0: WDT3 Clock Enabled (200MHz)
Cortex_R5_0: Enabling UART[0:5]/LIN[0:5] Clocks
Cortex_R5_0: LIN0_UART0 Clock Enabled (160MHz)
Cortex_R5_0: LIN1_UART1 Clock Enabled (160MHz)
Cortex_R5_0: LIN2_UART2 Clock Enabled (160MHz)
Cortex_R5_0: LIN3_UART3 Clock Enabled (160MHz)
Cortex_R5_0: LIN4_UART4 Clock Enabled (160MHz)
Cortex_R5_0: LIN5_UART5 Clock Enabled (160MHz)
Cortex_R5_0: Enabling QSPI Clocks
Cortex_R5_0: QSPI0 Clock Enabled (80MHz)
Cortex_R5_0: Enabling I2C Clocks
Cortex_R5_0: I2C Clock Enabled (48MHz)
Cortex_R5_0: Enabling TRACE Clocks
Cortex_R5_0: Trace Clock Enabled (250MHz)
Cortex_R5_0: Enabling MCAN[0:3] Clocks
Cortex_R5_0: MCAN0 Clock Enabled (80MHz)
Cortex_R5_0: MCAN1 Clock Enabled (80MHz)
Cortex_R5_0: MCAN2 Clock Enabled (80MHz)
Cortex_R5_0: MCAN3 Clock Enabled (80MHz)
Cortex_R5_0: Enabling GPMC Clocks
Cortex_R5_0: GPMC Clock Enabled (100MHz)
Cortex_R5_0: Enabling ELM Clocks
Cortex_R5_0: ELM Clock Enabled (50MHz)
Cortex_R5_0: Enabling MMCSD Clocks
Cortex_R5_0: MMCSD Clock Enabled (48MHz)
Cortex_R5_0: Enabling MCSPI[0:4] Clocks
Cortex_R5_0: MCSPI0 Clock Enabled (48MHz)
Cortex_R5_0: MCSPI1 Clock Enabled (48MHz)
Cortex_R5_0: MCSPI2 Clock Enabled (48MHz)
Cortex_R5_0: MCSPI3 Clock Enabled (48MHz)
Cortex_R5_0: MCSPI4 Clock Enabled (48MHz)
Cortex_R5_0: Enabling CONTROLSS Clocks
Cortex_R5_0: CONTROLSS Clock Enabled (400MHz)
Cortex_R5_0: Enabling CPTS Clocks
Cortex_R5_0: CPTS Clock Enabled (250MHz)
Cortex_R5_0: Enabling RGMI[5,50,250] Clocks
Cortex_R5_0: RGMII5 Clock Enabled (5MHz)
Cortex_R5_0: RGMII50 Clock Enabled (50MHz)
Cortex_R5_0: RGMII250 Clock Enabled (250MHz)
Cortex_R5_0: Enabling XTAL_TEMPSENSE_32K Clocks
Cortex_R5_0: TEMPSENSE Clock Enabled (32KHz)
Cortex_R5_0: Enabling XTAL_MMC_32K Clocks
Cortex_R5_0: XTAL_MMC Clock Enabled (32KHz)
Cortex_R5_0:

 ***All IP Clocks are Enabled***

Cortex_R5_0: CPU reset (soft reset) has been issued through GEL on program load.
Cortex_R5_1: CPU reset (soft reset) has been issued through GEL on program load.
Cortex_R5_2: CPU reset (soft reset) has been issued through GEL on program load.
Cortex_R5_3: CPU reset (soft reset) has been issued through GEL on program load.