// SPDX-License-Identifier: GPL-2.0 /* * DT Overlay for Fusion (FPD-Link III) board on J721E EVM * https://svtronics.com/portfolio/evm577pfusion-v1-0-fusion/ * * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; /plugin/; #include &{/} { clk_fusion_25M_fixed: fixed-clock-25M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; }; &main_i2c6 { #address-cells = <1>; #size-cells = <0>; status = "okay"; deser@3d { compatible = "ti,ds90ub960-q1"; reg = <0x3d>; clocks = <&clk_fusion_25M_fixed>; clock-names = "refclk"; i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; ds90ub960_0_ports: ports { #address-cells = <1>; #size-cells = <0>; /* CSI-2 TX */ port@4 { reg = <4>; ds90ub960_0_csi_out: endpoint { clock-lanes = <0>; data-lanes = <1 2 3 4>; link-frequencies = /bits/ 64 <800000000>; remote-endpoint = <&csi2_phy0>; }; }; }; ds90ub960_0_links: links { #address-cells = <1>; #size-cells = <0>; }; }; deser@36 { status = "disable"; compatible = "ti,ds90ub960-q1"; reg = <0x36>; clocks = <&clk_fusion_25M_fixed>; clock-names = "refclk"; i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; ds90ub960_1_ports: ports { #address-cells = <1>; #size-cells = <0>; /* CSI-2 TX */ port@4 { reg = <4>; ds90ub960_1_csi_out: endpoint { clock-lanes = <0>; data-lanes = <1 2 3 4>; link-frequencies = /bits/ 64 <800000000>; remote-endpoint = <&csi2_phy1>; }; }; }; ds90ub960_1_links: links { #address-cells = <1>; #size-cells = <0>; }; }; }; &csi0_port0 { status = "okay"; csi2_phy0: endpoint { remote-endpoint = <&ds90ub960_0_csi_out>; clock-lanes = <0>; data-lanes = <1 2 3 4>; link-frequencies = /bits/ 64 <800000000>; }; }; &csi1_port0 { status = "okay"; csi2_phy1: endpoint { remote-endpoint = <&ds90ub960_1_csi_out>; clock-lanes = <0>; data-lanes = <1 2 3 4>; link-frequencies = /bits/ 64 <800000000>; }; };