/* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /dts-v1/; #include "am33xx.dtsi" #include / { model = "TI AM335x EVM"; compatible = "ti,am335x-evm", "ti,am33xx"; memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; vbat: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; }; lis3_reg: fixedregulator@1 { compatible = "regulator-fixed"; regulator-name = "lis3_reg"; regulator-boot-on; }; wlan_en_reg: fixedregulator@2 { compatible = "regulator-fixed"; regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; /* WLAN_EN GPIO for this board - Bank3, pin9 */ gpio = <&gpio3 9 0>; /* WLAN card specific delay */ startup-delay-us = <70000>; enable-active-high; }; btwilink { compatible = "btwilink"; }; }; &am33xx_pinmux { pinctrl-names = "default"; jtag_pins_default: jtag_pins_default { pinctrl-single,pins = < 0x1d0 ( PIN_INPUT | MUX_MODE0 ) /* (C14) TMS.TMS */ 0x1d4 ( PIN_INPUT | MUX_MODE0 ) /* (B13) TDI.TDI */ 0x1d8 ( PIN_OUTPUT | MUX_MODE0 ) /* (A14) TDO.TDO */ 0x1dc ( PIN_INPUT | MUX_MODE0 ) /* (B14) TCK.TCK */ 0x1e0 ( PIN_INPUT | MUX_MODE0 ) /* (A13) nTRST.nTRST */ 0x1e4 ( PIN_INPUT | MUX_MODE0 ) /* (A15) EMU0.EMU0 */ 0x1e8 ( PIN_INPUT | MUX_MODE0 ) /* (D14) EMU1.EMU1 */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ jtag_pins_sleep: jtag_pins_sleep { pinctrl-single,pins = < 0x1d0 (PIN_INPUT_PULLDOWN ) /* (C14) TMS.TMS */ 0x1d4 (PIN_INPUT_PULLDOWN ) /* (B13) TDI.TDI */ 0x1d8 (PIN_INPUT_PULLDOWN ) /* (A14) TDO.TDO */ 0x1dc (PIN_INPUT_PULLDOWN ) /* (B14) TCK.TCK */ 0x1e0 (PIN_INPUT_PULLDOWN ) /* (A13) nTRST.nTRST */ 0x1e4 (PIN_INPUT_PULLDOWN ) /* (A15) EMU0.EMU0 */ 0x1e8 (PIN_INPUT_PULLDOWN ) /* (D14) EMU1.EMU1 */ >; }; gpio0_pins_default: gpio0_pins_default { pinctrl-single,pins = < 0x1b0 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (C15) xdma_event_intr0.gpio0[19] */ 0x24 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (W16) gpmc_ad9.gpio0[23] */ 0x28 ( PIN_OUTPUT | MUX_MODE7 ) /* (T12) gpmc_ad10.gpio0[26] */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ gpio0_pins_sleep: gpio0_pins_sleep { pinctrl-single,pins = < 0x1b0 (PIN_INPUT_PULLDOWN ) /* (C15) xdma_event_intr0.gpio0[19] */ 0x24 (PIN_INPUT_PULLDOWN ) /* (W16) gpmc_ad9.gpio0[23] */ 0x28 (PIN_INPUT_PULLDOWN ) /* (T12) gpmc_ad10.gpio0[26] */ >; }; gpio1_pins_default: gpio1_pins_default { pinctrl-single,pins = < 0x78 ( PIN_OUTPUT | MUX_MODE7 ) /* (V18) gpmc_be1n.gpio1[28] */ 0x80 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (V14) gpmc_csn1.gpio1[30] */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ gpio1_pins_sleep: gpio1_pins_sleep { pinctrl-single,pins = < 0x78 (PIN_INPUT_PULLDOWN ) /* (V18) gpmc_be1n.gpio1[28] */ 0x80 (PIN_INPUT_PULLDOWN ) /* (V14) gpmc_csn1.gpio1[30] */ >; }; gpio2_pins_default: gpio2_pins_default { pinctrl-single,pins = < 0x88 ( PIN_OUTPUT | MUX_MODE7 ) /* (U17) gpmc_csn3.gpio2[0] */ 0x8c ( PIN_OUTPUT | MUX_MODE7 ) /* (V16) gpmc_clk.gpio2[1] */ 0xa0 ( PIN_OUTPUT | MUX_MODE7 ) /* (U1) lcd_data0.gpio2[6] */ ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (U7) lcd_vsync.gpio2[22] */ 0xe4 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (T7) lcd_hsync.gpio2[23] */ 0xe8 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (W5) lcd_pclk.gpio2[24] */ 0xec ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (W7) lcd_ac_bias_en.gpio2[25] */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ gpio2_pins_sleep: gpio2_pins_sleep { pinctrl-single,pins = < 0x88 (PIN_INPUT_PULLDOWN ) /* (U17) gpmc_csn3.gpio2[0] */ 0x8c (PIN_INPUT_PULLDOWN ) /* (V16) gpmc_clk.gpio2[1] */ 0xa0 (PIN_INPUT_PULLDOWN ) /* (U1) lcd_data0.gpio2[6] */ 0xe0 (PIN_INPUT_PULLDOWN ) /* (U7) lcd_vsync.gpio2[22] */ 0xe4 (PIN_INPUT_PULLDOWN ) /* (T7) lcd_hsync.gpio2[23] */ 0xe8 (PIN_INPUT_PULLDOWN ) /* (W5) lcd_pclk.gpio2[24] */ 0xec (PIN_INPUT_PULLDOWN ) /* (W7) lcd_ac_bias_en.gpio2[25] */ >; }; gpio3_pins_default: gpio3_pins_default { pinctrl-single,pins = < 0x108 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (J19) gmii1_col.gpio3[0] */ 0x118 ( PIN_OUTPUT | MUX_MODE7 ) /* (L19) gmii1_rxdv.gpio3[4] */ 0x12c ( PIN_OUTPUT | MUX_MODE7 ) /* (N19) gmii1_txclk.gpio3[9] */ 0x130 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (M19) gmii1_rxclk.gpio3[10] */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ gpio3_pins_sleep: gpio3_pins_sleep { pinctrl-single,pins = < 0x108 (PIN_INPUT_PULLDOWN ) /* (J19) gmii1_col.gpio3[0] */ 0x118 (PIN_INPUT_PULLDOWN ) /* (L19) gmii1_rxdv.gpio3[4] */ 0x12c (PIN_INPUT_PULLDOWN ) /* (N19) gmii1_txclk.gpio3[9] */ 0x130 (PIN_INPUT_PULLDOWN ) /* (M19) gmii1_rxclk.gpio3[10] */ >; }; nand_pins_default: nand_pins_default { pinctrl-single,pins = < 0x1c ( PIN_INPUT | MUX_MODE0 ) /* (W15) gpmc_ad7.gpmc_ad7 */ 0x18 ( PIN_INPUT | MUX_MODE0 ) /* (U14) gpmc_ad6.gpmc_ad6 */ 0x14 ( PIN_INPUT | MUX_MODE0 ) /* (W14) gpmc_ad5.gpmc_ad5 */ 0x10 ( PIN_INPUT | MUX_MODE0 ) /* (V13) gpmc_ad4.gpmc_ad4 */ 0xc ( PIN_INPUT | MUX_MODE0 ) /* (W13) gpmc_ad3.gpmc_ad3 */ 0x8 ( PIN_INPUT | MUX_MODE0 ) /* (V12) gpmc_ad2.gpmc_ad2 */ 0x4 ( PIN_INPUT | MUX_MODE0 ) /* (V9) gpmc_ad1.gpmc_ad1 */ 0x0 ( PIN_INPUT | MUX_MODE0 ) /* (W10) gpmc_ad0.gpmc_ad0 */ 0x70 ( PIN_INPUT | MUX_MODE0 ) /* (R15) gpmc_wait0.gpmc_wait0 */ 0x74 ( PIN_OUTPUT | MUX_MODE0 ) /* (W18) gpmc_wpn.gpmc_wpn */ 0x7c ( PIN_OUTPUT | MUX_MODE0 ) /* (W8) gpmc_csn0.gpmc_csn0 */ 0x90 ( PIN_OUTPUT | MUX_MODE0 ) /* (V10) gpmc_advn_ale.gpmc_advn_ale */ 0x94 ( PIN_OUTPUT | MUX_MODE0 ) /* (W9) gpmc_oen_ren.gpmc_oen_ren */ 0x98 ( PIN_OUTPUT | MUX_MODE0 ) /* (U8) gpmc_wen.gpmc_wen */ 0x9c ( PIN_OUTPUT | MUX_MODE0 ) /* (V8) gpmc_be0n_cle.gpmc_be0n_cle */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ nand_pins_sleep: nand_pins_sleep { pinctrl-single,pins = < 0x1c ( PIN_INPUT_PULLDOWN ) /* (W15) gpmc_ad7.gpmc_ad7 */ 0x18 ( PIN_INPUT_PULLDOWN ) /* (U14) gpmc_ad6.gpmc_ad6 */ 0x14 ( PIN_INPUT_PULLDOWN ) /* (W14) gpmc_ad5.gpmc_ad5 */ 0x10 ( PIN_INPUT_PULLDOWN ) /* (V13) gpmc_ad4.gpmc_ad4 */ 0xc ( PIN_INPUT_PULLDOWN ) /* (W13) gpmc_ad3.gpmc_ad3 */ 0x8 ( PIN_INPUT_PULLDOWN ) /* (V12) gpmc_ad2.gpmc_ad2 */ 0x4 ( PIN_INPUT_PULLDOWN ) /* (V9) gpmc_ad1.gpmc_ad1 */ 0x0 ( PIN_INPUT_PULLDOWN ) /* (W10) gpmc_ad0.gpmc_ad0 */ 0x70 ( PIN_INPUT_PULLDOWN ) /* (R15) gpmc_wait0.gpmc_wait0 */ 0x74 ( PIN_INPUT_PULLDOWN ) /* (W18) gpmc_wpn.gpmc_wpn */ 0x7c ( PIN_INPUT_PULLDOWN ) /* (W8) gpmc_csn0.gpmc_csn0 */ 0x90 ( PIN_INPUT_PULLDOWN ) /* (V10) gpmc_advn_ale.gpmc_advn_ale */ 0x94 ( PIN_INPUT_PULLDOWN ) /* (W9) gpmc_oen_ren.gpmc_oen_ren */ 0x98 ( PIN_INPUT_PULLDOWN ) /* (U8) gpmc_wen.gpmc_wen */ 0x9c ( PIN_INPUT_PULLDOWN ) /* (V8) gpmc_be0n_cle.gpmc_be0n_cle */ >; }; mdio_pins_default: mdio_pins_default { pinctrl-single,pins = < 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_clk.mdio_clk */ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ mdio_pins_sleep: mdio_pins_sleep { pinctrl-single,pins = < 0x14c ( PIN_INPUT_PULLDOWN ) /* (R19) mdio_clk.mdio_clk */ 0x148 ( PIN_INPUT_PULLDOWN ) /* (P17) mdio_data.mdio_data */ >; }; rmii_pins_default: rmii_pins_default { pinctrl-single,pins = < 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ 0x110 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 0x13c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 0x140 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ rmii_pins_sleep: rmii_pins_sleep { pinctrl-single,pins = < 0x10c ( PIN_INPUT_PULLDOWN ) /* (J18) gmii1_crs.rmii1_crs_dv */ 0x110 ( PIN_INPUT_PULLDOWN ) /* (K19) gmii1_rxer.rmii1_rxer */ 0x114 ( PIN_INPUT_PULLDOWN ) /* (K17) gmii1_txen.rmii1_txen */ 0x128 ( PIN_INPUT_PULLDOWN ) /* (L18) gmii1_txd0.rmii1_txd0 */ 0x124 ( PIN_INPUT_PULLDOWN ) /* (M18) gmii1_txd1.rmii1_txd1 */ 0x140 ( PIN_INPUT_PULLDOWN ) /* (P18) gmii1_rxd0.rmii1_rxd0 */ 0x13c ( PIN_INPUT_PULLDOWN ) /* (P19) gmii1_rxd1.rmii1_rxd1 */ 0x144 ( PIN_INPUT_PULLDOWN ) /* (K18) rmii1_refclk.rmii1_refclk */ >; }; wlan_sdio_pins_default: wlan_sdio_pins_default { pinctrl-single,pins = < 0x100 ( PIN_INPUT | MUX_MODE0 ) /* (G19) mmc0_clk.mmc0_clk */ 0x104 ( PIN_OUTPUT | MUX_MODE0 ) /* (G17) mmc0_cmd.mmc0_cmd */ 0xfc ( PIN_INPUT | MUX_MODE0 ) /* (G18) mmc0_dat0.mmc0_dat0 */ 0xf8 ( PIN_INPUT | MUX_MODE0 ) /* (H17) mmc0_dat1.mmc0_dat1 */ 0xf4 ( PIN_INPUT | MUX_MODE0 ) /* (H18) mmc0_dat2.mmc0_dat2 */ 0xf0 ( PIN_INPUT | MUX_MODE0 ) /* (H19) mmc0_dat3.mmc0_dat3 */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ wlan_sdio_pins_sleep: wlan_sdio_pins_sleep { pinctrl-single,pins = < 0x100 ( PIN_INPUT_PULLDOWN ) /* (G19) mmc0_clk.mmc0_clk */ 0x104 ( PIN_INPUT_PULLDOWN ) /* (G17) mmc0_cmd.mmc0_cmd */ 0xfc ( PIN_INPUT_PULLDOWN ) /* (G18) mmc0_dat0.mmc0_dat0 */ 0xf8 ( PIN_INPUT_PULLDOWN ) /* (H17) mmc0_dat1.mmc0_dat1 */ 0xf4 ( PIN_INPUT_PULLDOWN ) /* (H18) mmc0_dat2.mmc0_dat2 */ 0xf0 ( PIN_INPUT_PULLDOWN ) /* (H19) mmc0_dat3.mmc0_dat3 */ >; }; i2c0_pins_default: i2c0_pins_default { pinctrl-single,pins = < 0x18c ( PIN_INPUT | MUX_MODE0 ) /* (B19) I2C0_SCL.I2C0_SCL */ 0x188 ( PIN_INPUT | MUX_MODE0 ) /* (C18) I2C0_SDA.I2C0_SDA */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ i2c0_pins_sleep: i2c0_pins_sleep { pinctrl-single,pins = < 0x18c ( PIN_INPUT_PULLDOWN ) /* (B19) I2C0_SCL.I2C0_SCL */ 0x188 ( PIN_INPUT_PULLDOWN ) /* (C18) I2C0_SDA.I2C0_SDA */ >; }; usb0_pins_default: usb0_pins_default { pinctrl-single,pins = < 0x21c ( PIN_OUTPUT | MUX_MODE0 ) /* (G16) USB0_DRVVBUS.USB0_DRVVBUS */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ usb0_pins_sleep: usb0_pins_sleep { pinctrl-single,pins = < 0x21c ( PIN_INPUT_PULLDOWN ) /* (G16) USB0_DRVVBUS.USB0_DRVVBUS */ >; }; spi0_pins_default: spi0_pins_default { pinctrl-single,pins = < 0x150 ( PIN_INPUT | MUX_MODE0 ) /* (A18) spi0_sclk.spi0_sclk */ 0x154 ( PIN_INPUT | MUX_MODE0 ) /* (B18) spi0_d0.spi0_d0 */ 0x158 ( PIN_INPUT | MUX_MODE0 ) /* (B17) spi0_d1.spi0_d1 */ 0x15c ( PIN_OUTPUT | MUX_MODE0 ) /* (A17) spi0_cs0.spi0_cs0 */ 0x160 ( PIN_OUTPUT | MUX_MODE0 ) /* (B16) spi0_cs1.spi0_cs1 */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ spi0_pins_sleep: spi0_pins_sleep { pinctrl-single,pins = < 0x150 ( PIN_INPUT_PULLDOWN ) /* (A18) spi0_sclk.spi0_sclk */ 0x154 ( PIN_INPUT_PULLDOWN ) /* (B18) spi0_d0.spi0_d0 */ 0x158 ( PIN_INPUT_PULLDOWN ) /* (B17) spi0_d1.spi0_d1 */ 0x15c ( PIN_INPUT_PULLDOWN ) /* (A17) spi0_cs0.spi0_cs0 */ 0x160 ( PIN_INPUT_PULLDOWN ) /* (B16) spi0_cs1.spi0_cs1 */ >; }; uart0_pins_default: uart0_pins_default { pinctrl-single,pins = < 0x170 ( PIN_INPUT | MUX_MODE0 ) /* (E19) uart0_rxd.uart0_rxd */ 0x174 ( PIN_OUTPUT | MUX_MODE0 ) /* (F17) uart0_txd.uart0_txd */ 0x168 ( PIN_INPUT | MUX_MODE0 ) /* (F19) uart0_ctsn.uart0_ctsn */ 0x16c ( PIN_OUTPUT | MUX_MODE0 ) /* (F18) uart0_rtsn.uart0_rtsn */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ uart0_pins_sleep: uart0_pins_sleep { pinctrl-single,pins = < 0x170 ( PIN_INPUT_PULLDOWN ) /* (E19) uart0_rxd.uart0_rxd */ 0x174 ( PIN_INPUT_PULLDOWN ) /* (F17) uart0_txd.uart0_txd */ 0x168 ( PIN_INPUT_PULLDOWN ) /* (F19) uart0_ctsn.uart0_ctsn */ 0x16c ( PIN_INPUT_PULLDOWN ) /* (F18) uart0_rtsn.uart0_rtsn */ >; }; uart1_pins_default: uart1_pins_default { pinctrl-single,pins = < 0x180 ( PIN_INPUT | MUX_MODE0 ) /* (D18) uart1_rxd.uart1_rxd */ 0x184 ( PIN_OUTPUT | MUX_MODE0 ) /* (C19) uart1_txd.uart1_txd */ 0x178 ( PIN_INPUT | MUX_MODE0 ) /* (E17) uart1_ctsn.uart1_ctsn */ 0x17c ( PIN_OUTPUT | MUX_MODE0 ) /* (D19) uart1_rtsn.uart1_rtsn */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ uart1_pins_sleep: uart1_pins_sleep { pinctrl-single,pins = < 0x180 ( PIN_INPUT_PULLDOWN ) /* (D18) uart1_rxd.uart1_rxd */ 0x184 ( PIN_INPUT_PULLDOWN ) /* (C19) uart1_txd.uart1_txd */ 0x178 ( PIN_INPUT_PULLDOWN ) /* (E17) uart1_ctsn.uart1_ctsn */ 0x17c ( PIN_INPUT_PULLDOWN ) /* (D19) uart1_rtsn.uart1_rtsn */ >; }; uart3_pins_default: uart3_pins_default { pinctrl-single,pins = < 0x134 ( PIN_INPUT | MUX_MODE1 ) /* (N17) gmii1_rxd3.uart3_rxd */ 0x138 ( PIN_OUTPUT | MUX_MODE1 ) /* (N16) gmii1_rxd2.uart3_txd */ 0xc8 ( PIN_INPUT | MUX_MODE6 ) /* (U5) lcd_data10.uart3_ctsn */ 0xcc ( PIN_OUTPUT | MUX_MODE6 ) /* (V5) lcd_data11.uart3_rtsn */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ uart3_pins_sleep: uart3_pins_sleep { pinctrl-single,pins = < 0x134 ( PIN_INPUT_PULLDOWN ) /* (N17) gmii1_rxd3.uart3_rxd */ 0x138 ( PIN_INPUT_PULLDOWN ) /* (N16) gmii1_rxd2.uart3_txd */ 0xc8 ( PIN_INPUT_PULLDOWN ) /* (U5) lcd_data10.uart3_ctsn */ 0xcc ( PIN_INPUT_PULLDOWN ) /* (V5) lcd_data11.uart3_rtsn */ >; }; uart4_pins_default: uart4_pins_default { pinctrl-single,pins = < 0x11c ( PIN_INPUT | MUX_MODE3 ) /* (M17) gmii1_txd3.uart4_rxd */ 0x120 ( PIN_OUTPUT | MUX_MODE3 ) /* (N18) gmii1_txd2.uart4_txd */ 0xd0 ( PIN_INPUT | MUX_MODE6 ) /* (V6) lcd_data12.uart4_ctsn */ 0xd4 ( PIN_OUTPUT | MUX_MODE6 ) /* (U6) lcd_data13.uart4_rtsn */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ uart4_pins_sleep: uart4_pins_sleep { pinctrl-single,pins = < 0x11c ( PIN_INPUT_PULLDOWN ) /* (M17) gmii1_txd3.uart4_rxd */ 0x120 ( PIN_INPUT_PULLDOWN ) /* (N18) gmii1_txd2.uart4_txd */ 0xd0 ( PIN_INPUT_PULLDOWN ) /* (V6) lcd_data12.uart4_ctsn */ 0xd4 ( PIN_INPUT_PULLDOWN ) /* (U6) lcd_data13.uart4_rtsn */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_default>; status = "okay"; }; &uart1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart1_pins_default>; pinctrl-1 = <&uart1_pins_sleep>; status = "okay"; }; &uart3 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart3_pins_default>; pinctrl-1 = <&uart3_pins_sleep>; status = "okay"; }; &uart4 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart4_pins_default>; pinctrl-1 = <&uart4_pins_sleep>; status = "okay"; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_default>; }; &usb { status = "okay"; }; &usb_ctrl_mod { status = "okay"; }; &usb0_phy { status = "okay"; }; &cppi41dma { status = "okay"; }; &elm { status = "okay"; }; &gpmc { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&nand_pins_default>; pinctrl-1 = <&nand_pins_sleep>; ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&intc>; interrupts = <100>; ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <40>; gpmc,oe-on-ns = <0>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x000020000>; }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00020000 0x00020000>; }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00040000 0x00020000>; }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x00060000 0x00020000>; }; partition@4 { label = "NAND.u-boot-spl-os"; reg = <0x00080000 0x00040000>; }; partition@5 { label = "NAND.u-boot"; reg = <0x000C0000 0x00100000>; }; partition@6 { label = "NAND.u-boot-env"; reg = <0x001C0000 0x00020000>; }; partition@7 { label = "NAND.u-boot-env.backup1"; reg = <0x001E0000 0x00020000>; }; partition@8 { label = "NAND.kernel"; reg = <0x00200000 0x00800000>; }; partition@9 { label = "NAND.file-system"; reg = <0x00A00000 0x0F600000>; }; }; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&rmii_pins_default>; pinctrl-1 = <&rmii_pins_sleep>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&mdio_pins_default>; pinctrl-1 = <&mdio_pins_sleep>; status = "okay"; }; &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; phy-mode = "rmii"; }; &cpsw_emac1 { phy_id = <&davinci_mdio>, <1>; phy-mode = "rmii"; }; &phy_sel { rmii-clock-ext; }; &mmc1 { dmas = <&edma 12 &edma 13>; dma-names = "tx", "rx"; status = "okay"; vmmc-supply = <&wlan_en_reg>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&wlan_sdio_pins_default>; pinctrl-1 = <&wlan_sdio_pins_sleep>; ti,non-removable; ti,needs-special-hs-handling; cap-power-off-card; keep-power-in-suspend; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio3>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; ref-clock-frequency = <38400000>; }; }; &edma { ti,edma-xbar-event-map = /bits/ 16 <1 12 2 13>; }; &sham { status = "okay"; }; &aes { status = "okay"; }; &wkup_m3_ipc { ti,scale-data-fw = "am335x-evm-scale-data.bin"; }; &rtc { system-power-controller; }; &sgx { status = "okay"; };