1. DDR init with nanya parameters

2. pll12 0068c000-0068c080

reg[0x68c000]:val[0x61801001]
reg[0x68c008]:val[0x10801]
reg[0x68c010]:val[0x68ef3491]
reg[0x68c014]:val[0xd172bc5a]
reg[0x68c020]:val[0x18013]
reg[0x68c024]:val[0x1]
reg[0x68c030]:val[0x4a]
reg[0x68c034]:val[0xa8f5c3]
reg[0x68c038]:val[0x1010001]
reg[0x68c040]:val[0x80000000]
reg[0x68c044]:val[0x10001]
reg[0x68c060]:val[0x120000]
reg[0x68c064]:val[0xe7a]
reg[0x68c080]:val[0x8001]

3. MR5 read ID

4. ddr_reset

5. pll12 0068c000-0068c080

reg[0x68c000]:val[0x61801001]
reg[0x68c008]:val[0x10801]
reg[0x68c010]:val[0x68ef3491]
reg[0x68c014]:val[0xd172bc5a]
reg[0x68c020]:val[0x18013]
reg[0x68c024]:val[0x1]
reg[0x68c030]:val[0x4a]
reg[0x68c034]:val[0xa8f5c3]
reg[0x68c038]:val[0x1010001]
reg[0x68c040]:val[0x80000000]
reg[0x68c044]:val[0x10001]
reg[0x68c060]:val[0x120000]
reg[0x68c064]:val[0xe7a]
reg[0x68c080]:val[0x8001]

6. NANYA DRR parameters

reg[0x68c000]:val[0x61801001]
reg[0x68c008]:val[0x10801]
reg[0x68c010]:val[0x68ef3491]
reg[0x68c014]:val[0xd172bc5a]
reg[0x68c020]:val[0x18013]
reg[0x68c024]:val[0x1]
reg[0x68c030]:val[0x4a]
reg[0x68c034]:val[0xa8f5c3]
reg[0x68c038]:val[0x1010001]
reg[0x68c040]:val[0x80000000]
reg[0x68c044]:val[0x10001]
reg[0x68c060]:val[0x120000]
reg[0x68c064]:val[0xe7a]
reg[0x68c080]:val[0x8001]

7. memtester  success