root@am57xx-evm:~# ./om OMAPCONF (rev v1.74-1-g40ab0a2 built Wed Aug 17 07:11:49 UTC 2022) HW Platform: Generic DRA72X (Flattened Device Tree) DRA72X ES2.0 GP Device (STANDARD performance (1.5GHz)) Error: I2C Read failed Error: I2C Read failed Error: I2C Read failed TPS65917 ES UNKNOWN SW Build Details: Build: Version: _____ _____ _ _ Kernel: Version: 4.19.94-gbe5389fd85 Author: am5718@d7428f1f8d67 Toolchain: gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36) Type: #272 SMP PREEMPT Date: Wed Oct 12 18:26:31 KST 2022 |--------------------------------------------| | Reg. Name | Reg. Addr | Reg. Val. | |--------------------------------------------| | MCASP_PID | 0x48460000 | 0x44307B03 | | PWRIDLESYSCONFIG | 0x48460004 | 0x00000002 | | MCASP_PFUNC | 0x48460010 | 0x00000000 | | MCASP_PDIR | 0x48460014 | 0x00000001 | | MCASP_PDOUT | 0x48460018 | 0x00000000 | | MCASP_PDIN | 0x4846001C | 0x10000001 | | MCASP_PDCLR | 0x48460020 | 0x00000000 | | MCASP_GBLCTL | 0x48460044 | 0x00001F00 | | MCASP_AMUTE | 0x48460048 | 0x00000000 | | MCASP_LBCTL | 0x4846004C | 0x00000000 | | MCASP_TXDITCTL | 0x48460050 | 0x00000000 | | MCASP_GBLCTLR | 0x48460060 | 0x00001F00 | | MCASP_RXMASK | 0x48460064 | 0x0000FFFF | | MCASP_RXFMT | 0x48460068 | 0x000100F4 | | MCASP_RXFMCTL | 0x4846006C | 0x00000011 | | MCASP_ACLKRCTL | 0x48460070 | 0x00180080 | | MCASP_AHCLKRCTL | 0x48460074 | 0x00180000 | | MCASP_RXTDM | 0x48460078 | 0x00000000 | | MCASP_EVTCTLR | 0x4846007C | 0x00000000 | | MCASP_RXSTAT | 0x48460080 | 0x00000104 | | MCASP_RXTDMSLOT | 0x48460084 | 0x00000000 | | MCASP_RXCLKCHK | 0x48460088 | 0x00000000 | | MCASP_REVTCTL | 0x4846008C | 0x00000000 | | MCASP_GBLCTLX | 0x484600A0 | 0x00001F00 | | MCASP_TXMASK | 0x484600A4 | 0x0000FFFF | | MCASP_TXFMT | 0x484600A8 | 0x000180F4 | | MCASP_TXFMCTL | 0x484600AC | 0x00000111 | | MCASP_ACLKXCTL | 0x484600B0 | 0x000000C0 | | MCASP_AHCLKXCTL | 0x484600B4 | 0x00000000 | | MCASP_TXTDM | 0x484600B8 | 0x00000003 | | MCASP_EVTCTLX | 0x484600BC | 0x00000001 | | MCASP_TXSTAT | 0x484600C0 | 0x0000015C | | MCASP_TXTDMSLOT | 0x484600C4 | 0x00000001 | | MCASP_TXCLKCHK | 0x484600C8 | 0xA8000000 | | MCASP_XEVTCTL | 0x484600CC | 0x00000000 | | MCASP_CLKADJEN | 0x484600D0 | 0x00000000 | | MCASP_XRSRCTL0 | 0x48460180 | 0x00000009 | | MCASP_XRSRCTL1 | 0x48460184 | 0x00000008 | | MCASP_XRSRCTL2 | 0x48460188 | 0x00000000 | | MCASP_XRSRCTL3 | 0x4846018C | 0x00000000 | | MCASP_XRSRCTL4 | 0x48460190 | 0x00000000 | | MCASP_XRSRCTL5 | 0x48460194 | 0x00000000 | | MCASP_XRSRCTL6 | 0x48460198 | 0x00000000 | | MCASP_XRSRCTL7 | 0x4846019C | 0x00000000 | | MCASP_XRSRCTL8 | 0x484601A0 | 0x00000000 | | MCASP_XRSRCTL9 | 0x484601A4 | 0x00000000 | | MCASP_XRSRCTL10 | 0x484601A8 | 0x00000000 | | MCASP_XRSRCTL11 | 0x484601AC | 0x00000000 | | MCASP_XRSRCTL12 | 0x484601B0 | 0x00000000 | | MCASP_XRSRCTL13 | 0x484601B4 | 0x00000000 | | MCASP_XRSRCTL14 | 0x484601B8 | 0x00000000 | | MCASP_XRSRCTL15 | 0x484601BC | 0x00000000 | | MCASP_WFIFOCTL | 0x48461000 | 0x00012001 | | MCASP_WFIFOSTS | 0x48461004 | 0x00000024 | | MCASP_RFIFOCTL | 0x48461008 | 0x00000000 | | MCASP_RFIFOSTS | 0x4846100C | 0x00000000 | |--------------------------------------------| root@am57xx-evm:~# omapconf show mcasp1 OMAPCONF (rev v1.74-1-g40ab0a2 built Wed Aug 17 07:11:49 UTC 2022) HW Platform: Generic DRA72X (Flattened Device Tree) DRA72X ES2.0 GP Device (STANDARD performance (1.5GHz)) Error: I2C Read failed Error: I2C Read failed Error: I2C Read failed TPS65917 ES UNKNOWN SW Build Details: Build: Version: _____ _____ _ _ Kernel: Version: 4.19.94-gbe5389fd85 Author: am5718@d7428f1f8d67 Toolchain: gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36) Type: #272 SMP PREEMPT Date: Wed Oct 12 18:26:31 KST 2022 |---------------------------------------------| | Data Ports and Buffers | |---------------------------------------------| | Port | DATA bus | | Transmit DMA | | | DMA request | Enabled | | Status | No error | | Receive DMA | | | DMA request | Enabled | | Status | No error | | Transmit Buffer (XBUF) | | | Status | No error | | Receive Buffer (RBUF) | | | Status | No error | | Write FIFO (WFIFO) | | | State | Enabled | | Threshold | 32 samples | | Level | 40 samples in FIFO | | Read FIFO (RFIFO) | | | State | Disabled | | Threshold | 0 samples | | Level | 0 samples in FIFO | |---------------------------------------------| |----------------------------------------| | Control | |----------------------------------------| | Transmit State-Machine | | | State | Active | | Transmit Sequencer | | | Enabled Slots | 2 | | Active Slots | 2 | | Active Slots Mask | 0x00000003 | | Current Slot | 0 | | Receive State-Machine | | | State | Held in reset | | Receive Sequencer | | | Enabled Slots | INVALID | | Active Slots | 0 | | Active Slots Mask | 0x00000000 | | Current Slot | Inactive | |----------------------------------------| |----------------------------------------------------| | Clocks | |----------------------------------------------------| | Transmit Bit Clock | | | State | Running | | Divider | Divide-by 1 | | Source | External (ACLKX pin) | | Polarity | Driven on falling edge | | Transmit High-Speed Clock | | | State | Running | | Divider | Divide-by 1 | | Source | External (AHCLKX pin) | | Polarity | Non-inverted | | Receive Bit Clock | | | State | Held in reset | | Divider | Divide-by 1 | | Source | External (ACLKR pin) | | Polarity | Samples on rising edge | | Receive High-Speed Clock | | | State | Held in reset | | Divider | Divide-by 1 | | Source | External (AHCLKR pin) | | Polarity | Non-inverted | | Sync Mode | Synchronous to TX | | Idle Mode | Smart-idle | |----------------------------------------------------| |----------------------------------------------------| | Frame Sync Generator | |----------------------------------------------------| | Transmit Frame Sync | | | Generator State | Active | | Source | External | | Polarity | Frame starts on falling edge | | Pulse Width | Single word | | Slot Count | 2 (TDM) | | Data Delay | 1-bit | | Status | No error | | Receive Frame Sync | | | Generator State | Held in reset | | Source | External | | Polarity | Frame starts on falling edge | | Pulse Width | Single word | | Slot Count | INVALID | | Data Delay | 1-bit | | Status | No error | | Sync Mode | Synchronous to TX | |----------------------------------------------------| |-----------------------------------------| | Format Units | |-----------------------------------------| | Transmit Format Unit | | | Slot Size | 32 bits | | Bit Mask | 0x0000FFFF | | Padding | Pad with 0 | | Right-Rotation | 16 bit positions | | Bitstream Order | MSB first | | Receive Format Unit | | | Slot Size | 32 bits | | Bit Mask | 0x0000FFFF | | Padding | Pad with 0 | | Right-Rotation | 16 bit positions | | Bitstream Order | LSB first | |-----------------------------------------| |----------------------------------| | Serializers | |----------------------------------| | Transmit Serializers | Active | | Receive Serializers | Cleared | | Serializer 0 | | | Mode | Transmit | | Inactive State | Logic Low | | Serializer 1 | | | Mode | Inactive | | Inactive State | Logic Low | | Serializer 2 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 3 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 4 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 5 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 6 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 7 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 8 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 9 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 10 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 11 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 12 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 13 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 14 | | | Mode | Inactive | | Inactive State | Hi-Z | | Serializer 15 | | | Mode | Inactive | | Inactive State | Hi-Z | |----------------------------------| |--------------------------------------------| | Pin Control | |--------------------------------------------| | AFSR | | | Functionality | Receive Frame Sync | | Direction | Input | | ACLKR | | | Functionality | Receive Bit Clock | | Direction | Input | | AFSX | | | Functionality | Transmit Frame Sync | | Direction | Input | | ACLKX | | | Functionality | Transmit Bit Clock | | Direction | Input | | AHCLKX | | | Functionality | Transmit High-Freq Clock | | Direction | Input | | AXR0 | | | Functionality | TX/RX Data Channel 0 | | Direction | Output | | AXR1 | | | Functionality | TX/RX Data Channel 1 | | Direction | Input | | AXR2 | | | Functionality | TX/RX Data Channel 2 | | Direction | Input | | AXR3 | | | Functionality | TX/RX Data Channel 3 | | Direction | Input | | AXR4 | | | Functionality | TX/RX Data Channel 4 | | Direction | Input | | AXR5 | | | Functionality | TX/RX Data Channel 5 | | Direction | Input | | AXR6 | | | Functionality | TX/RX Data Channel 6 | | Direction | Input | | AXR7 | | | Functionality | TX/RX Data Channel 7 | | Direction | Input | | AXR8 | | | Functionality | TX/RX Data Channel 8 | | Direction | Input | | AXR9 | | | Functionality | TX/RX Data Channel 9 | | Direction | Input | | AXR10 | | | Functionality | TX/RX Data Channel 10 | | Direction | Input | | AXR11 | | | Functionality | TX/RX Data Channel 11 | | Direction | Input | | AXR12 | | | Functionality | TX/RX Data Channel 12 | | Direction | Input | | AXR13 | | | Functionality | TX/RX Data Channel 13 | | Direction | Input | | AXR14 | | | Functionality | TX/RX Data Channel 14 | | Direction | Input | | AXR15 | | | Functionality | TX/RX Data Channel 15 | | Direction | Input | |--------------------------------------------|