/**********************************************************************************************************************
* Device tree setting 
*
***********************************************************************************************************************/
My own am57xx_custom.dtsi added in am57xx-beagle-x15.dts file. below setting in am57xx_custom.dtsi

&dra7_pmx_core {
	cpsw_pins_default: cpsw_pins_default {
		pinctrl-single,pins = <
			/* Slave at addr 0x0 */
			DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE1)		/* rgmii0_td3.rmii0_crs(ball number ---> V7 */
			DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE1)		/* rgmii0_td2.rmii0_txen  ---> V3 */
			DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE1)		/* rgmii0_td1.rmii0_txd1  ---> Y2 */
			DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE1)		/* rgmii0_td0.rmii0_txd0  ---> W2 */
			
			DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE1) 	/* rgmii0_rd2.rmii0_rxer  ---> U7 */
			DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE1) 	/* rgmii0_rd1.rmii0_rxd1  ---> V6 */
			DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE1) 	/* rgmii0_rd0.rmii0_rxd0  ---> U6 */

			
			DRA7XX_CORE_IOPAD(0x3644, PIN_INPUT_PULLUP | MUX_MODE0) 	/* RMII_MHZ_50_CLK   --> U3*/
			
			/* Slave at addr 0x1 */

			DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT | MUX_MODE2)		/* UART3_RXD.rmii1_crs   ---> V2 */
			DRA7XX_CORE_IOPAD(0x3668, PIN_OUTPUT | MUX_MODE2)		/* RGMII0_RXC.rmii1_txen  ---> U5 */
			DRA7XX_CORE_IOPAD(0x366C, PIN_OUTPUT | MUX_MODE2)		/* RGMII0_RXCTL.rmii1_txd1  ---> V5 */
			DRA7XX_CORE_IOPAD(0x3670, PIN_OUTPUT | MUX_MODE2)		/* RGMII0_RXD3.rmii1_txd0  ---> V4 */
			
			DRA7XX_CORE_IOPAD(0x364C, PIN_INPUT_PULLDOWN | MUX_MODE2) 	/* UART3_TXD.rmii1_rxer  ---> Y1 */
			DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT_PULLDOWN | MUX_MODE2) 	/* RGMII0_TXC.rmii1_rxd1  ---> W9*/
			DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT_PULLDOWN | MUX_MODE2) 	/* RGMII0_TXCTL.rmii1_rxd0  ---> V9 */

			>;
		};
			

	cpsw_pins_sleep: cpsw_pins_sleep {
		pinctrl-single,pins = <
			/* Slave 1 */
			DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x365C, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x367C, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3644, PIN_INPUT_PULLDOWN | MUX_MODE15)

			/* Slave 2 */
			DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x366C, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x364C, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT_PULLDOWN | MUX_MODE15)
			
		>;
	};

	davinci_mdio_pins_default: davinci_mdio_pins_default {
		pinctrl-single,pins = <
			/* MDIO */
			DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* vin2a_d10.mdio_mclk */
			DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE0)	/* vin2a_d11.mdio_d */
		>;
	};

	davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLDOWN | MUX_MODE15)
		>;
	};
};



&mac {
	pinctrl-names = "default", "sleep";
        pinctrl-0 = <&cpsw_pins_default>;
        pinctrl-1 = <&cpsw_pins_sleep>;
        status = "okay";
	active_slave = <1>;
        dual_emac;
};

&cpsw_emac0 {
        phy-handle = <&phy0>;
	 phy-mode = "rmii";
       dual_emac_res_vlan = <0>;
};

&cpsw_emac1 {
       phy-handle = <&phy1>;
        phy-mode = "rmii";
        dual_emac_res_vlan = <1>;

};

&davinci_mdio {
        status = "okay";                                
	pinctrl-names = "default", "sleep";
        pinctrl-0 = <&davinci_mdio_pins_default>;
	pinctrl-1 = <&davinci_mdio_pins_sleep>;
	
        phy0: ethernet-phy@0 {
                reg = <0>;
        };

        phy1: ethernet-phy@1 {
                reg = <1>;
        };
};


In dra7.dtsi file for configure the address
 mac: ethernet@48484000 {
                        compatible = "ti,dra7-cpsw","ti,cpsw";
                        ti,hwmods = "gmac";
                        clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>;
                        clock-names = "fck", "cpts";
                        cpdma_channels = <8>;
                        ale_entries = <1024>;
                        bd_ram_size = <0x2000>;
                        mac_control = <0x20>;
                        slaves = <2>;
                        active_slave = <0>;
                        cpts_clock_mult = <0x784CFE14>;
                        cpts_clock_shift = <29>;
                        reg = <0x48484000 0x1000
                               0x48485200 0x2E00>;
                        #address-cells = <1>;
                        #size-cells = <1>;

                        /*
                         * Do not allow gating of cpsw clock as workaround
                         * for errata i877. Keeping internal clock disabled
                         * causes the device switching characteristics
                         * to degrade over time and eventually fail to meet
                         * the data manual delay time/skew specs.
                         */
                        ti,no-idle;

                        /*
                         * rx_thresh_pend
                         * rx_pend
                         * tx_pend
                         * misc_pend
                         */
                        interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
                        ranges;
                        syscon = <&scm_conf>;
                        status = "disabled";

                        davinci_mdio: mdio@48485000 {
                                compatible = "ti,cpsw-mdio","ti,davinci_mdio";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                ti,hwmods = "davinci_mdio";
                                bus_freq = <1000000>;
                                reg = <0x48485000 0x100>;
                        };

                        cpsw_emac0: slave@48480200 {
                                /* Filled in by U-Boot */
                                mac-address = [ 00 00 00 00 00 00 ];
                        };

                        cpsw_emac1: slave@48480300 {
                                /* Filled in by U-Boot */
                                mac-address = [ 00 00 00 00 00 00 ];
                        };

                        phy_sel: cpsw-phy-sel@4a002554 {
                                compatible = "ti,dra7xx-cpsw-phy-sel";
                                reg= <0x4a002554 0x4>;
                                reg-names = "gmii-sel";
                        };
                };