/*
 *  ======== rsc_table_omapl138.h ========
 *
 *  Include this table in each base image, which is read from remoteproc on
 *  host side.
 *
 */

#ifndef _RSC_TABLE_OMAPL138_H_
#define _RSC_TABLE_OMAPL138_H_

#include "rsc_types.h"

/* DSP Memory Map */
#define L3_CBA_RAM_BASE        (0x80000000)
#define IRAM_BASE              (0x11800000)
#define DSP_MEM_DATA           (0xc6100000)
#define STREAMING_DATA         (0xc7030000)

#define DSP_MEM_IPC_DATA       (0xc6800000)

#define DSP_MEM_IPC_VRING      (0xc6000000)
#define DSP_MEM_RPMSG_VRING0   (0xc6000000)
#define DSP_MEM_RPMSG_VRING1   (0xc6004000)
#define DSP_MEM_VRING_BUFS0    (0xc6040000)
#define DSP_MEM_VRING_BUFS1    (0xc6080000)

#define RPMSG_VRING_ADDR_ANY FW_RSC_ADDR_ANY

/* Sizes */
#define L3_CBA_RAM_SIZE        (0x20000)
#define IRAM_SIZE              (0x20000)
#define STREAMING_DATA_SIZE    (0x600000)
#define TRACEBUFSIZE           (0x20000)

#define DSP_MEM_DATA_SIZE      (SZ_1M * 15)
// #define DSP_MEM_IPC_VRING_SIZE (SZ_1M * 1)
// #define DSP_MEM_IPC_DATA_SIZE  (SZ_1M * 1)
#define DSP_MEM_IPC_VRING_SIZE (0x8000)
#define DSP_MEM_IPC_DATA_SIZE  (0x8000)

/*
 * The following values need to match Linux side device tree reserved
 * memory region start address for specific processor core.
 * The addresses are used to create mmu entry for IPC vrings and buffers
 */
#if defined (VAYU_DSP_1)
#define PHYS_MEM_IPC_VRING      0x99000000
#elif defined (VAYU_DSP_2)
#define PHYS_MEM_IPC_VRING      0x9F000000
#endif

/*
 * sizes of the virtqueues (expressed in number of buffers supported,
 * and must be power of 2)
 */
#define RPMSG_VQ0_SIZE          256
#define RPMSG_VQ1_SIZE          256

/* flip up bits whose indices represent features we support */
#define RPMSG_DSP_FEATURES      1

/* Amount of rsc table entries */
#define NUM_RSC_ENTRIES 7

struct my_resource_table {
    struct resource_table base;

    UInt32 offset[NUM_RSC_ENTRIES];

    /* rpmsg vdev entry */
    struct fw_rsc_vdev rpmsg_vdev;
    struct fw_rsc_vdev_vring rpmsg_vring0;
    struct fw_rsc_vdev_vring rpmsg_vring1;

    /* ipcdata carveout entry */
    struct fw_rsc_carveout ipcdata_cout;

    /* data carveout entry */
    struct fw_rsc_carveout data_cout;

    /* iram carveout entry */
    struct fw_rsc_carveout iram_cout;

    /* shared mem carveout entry */
    struct fw_rsc_carveout sm;

    /* streaming data carveout entry */
    struct fw_rsc_carveout streaming_data_cout;

    /* trace entry */
    struct fw_rsc_trace trace;

    /* devmem entry */
    // struct fw_rsc_devmem devmem0;
};

/* Add trace buffer information to the resource table */
extern char * xdc_runtime_SysMin_Module_State_0_outbuf__A;
#define TRACEBUFADDR (UInt32)&xdc_runtime_SysMin_Module_State_0_outbuf__A

#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)

struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
    1, /* we're the first version that implements this */
    NUM_RSC_ENTRIES, /* number of entries in the table */
    0, 0, /* reserved, must be zero */

    /* offsets to entries */
    {
        offsetof(struct my_resource_table, rpmsg_vdev),
        offsetof(struct my_resource_table, ipcdata_cout),
        offsetof(struct my_resource_table, data_cout),
        offsetof(struct my_resource_table, iram_cout),
        offsetof(struct my_resource_table, streaming_data_cout),
        offsetof(struct my_resource_table, sm),
        offsetof(struct my_resource_table, trace),
        // offsetof(struct my_resource_table, devmem0),
    },

    /* rpmsg vdev entry */
    {
        TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
        RPMSG_DSP_FEATURES, 0, 0, 0, 2, { 0, 0 },
        /* no config data */
    },
    /* the two vrings */
    { DSP_MEM_RPMSG_VRING0, 4096, RPMSG_VQ0_SIZE, 1, 0 },
    { DSP_MEM_RPMSG_VRING1, 4096, RPMSG_VQ1_SIZE, 2, 0 },

    {
        TYPE_CARVEOUT,
        DSP_MEM_IPC_DATA, 0,
        DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_DATA, DSP_MEM_DATA,
        DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
    },

    {
        TYPE_CARVEOUT,
        IRAM_BASE, IRAM_BASE,
        IRAM_SIZE, 0, 0, "IRAM",
    },

    {
        TYPE_CARVEOUT,
        L3_CBA_RAM_BASE, L3_CBA_RAM_BASE,
        L3_CBA_RAM_SIZE, 0, 0, "SHARED_MEM",
    },

    {
        TYPE_CARVEOUT,
        STREAMING_DATA, STREAMING_DATA,
        STREAMING_DATA_SIZE, 0, 0, "STREAMING_DATA",
    },

    {
        TYPE_TRACE,
        TRACEBUFADDR,
        TRACEBUFSIZE, 0, "trace:dsp",
    },

    // {
    //     TYPE_DEVMEM,
    //     DSP_MEM_IPC_VRING, DSP_MEM_IPC_VRING,
    //     DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
    // },
};

#endif /* _RSC_TABLE_OMAPL138_H_ */