/* * Copyright (c) 2013, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * ======== TMS320F28032.cmd ======== * Define the memory block start/length for the F28032 */ /* * PAGE 0 will be used to organize program sections * PAGE 1 will be used to organize data sections * * Notes: * Memory blocks on F2803x are uniform (ie same * physical memory) in both PAGE 0 and PAGE 1. * That is the same memory region should not be * defined for both PAGE 0 and PAGE 1. * Doing so will result in corruption of program * and/or data. * * L0 memory blocks are mirrored - that is * they can be accessed in high memory or low memory. * For simplicity only one instance is used in this * linker file. */ _Cla1Prog_Start = _CLAfuncsRunStart; -heap 0x200 -stack 0x200 // Define a size for the CLA scratchpad area that will be used // by the CLA compiler for local symbols and temps // Also force references to the special symbols that mark the // scratchpad are. CLA_SCRATCHPAD_SIZE = 0x100; --undef_sym=__cla_scratchpad_end --undef_sym=__cla_scratchpad_start MEMORY { PAGE 0: /* Program Memory */ //OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */ //FLASHH : origin = 0x3F0000, length = 0x000FFF /* on-chip FLASH */ //FLASHG : origin = 0x3F1000, length = 0x000FFF /* on-chip FLASH */ //FLASHF : origin = 0x3F2000, length = 0x000FFF /* on-chip FLASH */ //FLASHE : origin = 0x3F3000, length = 0x000FFF /* on-chip FLASH */ //FLASHD : origin = 0x3F4000, length = 0x000FFF /* on-chip FLASH */ //FLASHC : origin = 0x3F5000, length = 0x000FFF /* on-chip FLASH */ //FLASHB : origin = 0x3F6000, length = 0x000F7F /* on-chip FLASH */ BEGIN : origin = 0x3E8000, length = 0x000050 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ FLASH_PROG : origin = 0x3E8050, length = 0x00CFAD //, fill = 0xFFFF FLASH_CLA : origin = 0x3F4FFD, length = 0x000FFF //, fill = 0xFFFF CHECKUM : origin = 0x3F5FFD, length = 0x000002 //Where the code checksum is stored. //FLASHA : origin = 0x3F7000, length = 0x000F7F /* on-chip FLASH */ //CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ //BEGIN : origin = 0x3F6FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ //CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */ IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */ IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */ //ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ //VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ //L0SARAM_COPY : origin = 0x3F8000, length = 0x000800 /* A check to make sure Program flash doesn't overlap in this section */ L3SARAM : origin = 0x009000, length = 0x000FFF, //fill = 0xFFFF /* RAM Reserved for CLA */ PAGE 1 : /* Data Memory */ M01SARAM : origin = 0x000000, length = 0x000800, //fill = 0x0000 /* FAST RAM on-chip RAM block M0, M1 */ //PIEVECT : origin = 0x000D00, length = 0x000100 //L0SARAM : origin = 0x008000, length = 0x000800 /* SLOWER RAM on-chip RAM block L0 */ L01SARAM : origin = 0x008000, length = 0x000C00 //L0_SARAM : origin = 0x3F8000, length = 0x000800 //CLARAM0 : origin = 0x008800, length = 0x000400 CLARAM1 : origin = 0x008C00, length = 0x000400 CLA_CPU_MSGRAM : origin = 0x001480, length = 0x000080 /* CLA-R/W, CPU-R message RAM */ CPU_CLA_MSGRAM : origin = 0x001500, length = 0x000080 /* CPU-R/W, CLA-R message RAM */ } /* * Allocate sections to memory blocks. * Note: * codestart user defined section in DSP28_CodeStartBranch.asm * used to redirect code execution when booting to flash * * ramfuncs user defined section to store functions that will be * copied from Flash into RAM */ SECTIONS { /* Allocate program areas: */ .cinit : > FLASH_PROG PAGE = 0 .pinit : > FLASH_PROG PAGE = 0 .text : > FLASH_PROG PAGE = 0 codestart : > BEGIN PAGE = 0 .boot > BEGIN PAGE = 0 { -l rts2800_ml.lib(.text) } ramfuncs : LOAD = FLASH_PROG PAGE = 0, RUN = M01SARAM PAGE = 1, LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart) //{ //Used for SFRA library but something seems off, so it's commented out for now... // --library=rts2800_ml.lib // --library=SFRA_IQ_Lib.lib // --library=SFRA_IQ_Lib.lib //} controlfuncs : LOAD = FLASH_PROG PAGE = 0, RUN = L01SARAM PAGE = 1, LOAD_START(_ControlfuncsLoadStart), LOAD_SIZE(_ControlfuncsLoadSize), LOAD_END(_ControlfuncsLoadEnd), RUN_START(_ControlfuncsRunStart) /* CLATables : LOAD = FLASH_CLA PAGE = 0, RUN = CLARAM1 PAGE = 1, LOAD_START(_CLATablesLoadStart), LOAD_SIZE(_CLATablesLoadSize), LOAD_END(_CLATablesLoadEnd), RUN_START(_CLATablesRunStart) { CLA1mathTables .const_cla } */ //csmpasswds : > CSM_PWL PAGE = 0 //csm_rsvd : > CSM_RSVD PAGE = 0 /* Allocate uninitalized data sections: */ .stack : > M01SARAM PAGE = 1 // | L03SARAM //PAGE = 1 .ebss : > L01SARAM PAGE = 1 //| L03SARAM //PAGE = 1 .esysmem : > L01SARAM PAGE = 1 //| M01SARAM //PAGE = 1 .cio : > M01SARAM PAGE = 1 //| M01SARAM //PAGE = 1 .reset : > RESET, PAGE = 0, TYPE = DSECT /* Initalized sections go in Flash */ /* For SDFlash to program these, they must be allocated to page 0 */ .econst : > FLASH_PROG PAGE = 0 .switch : > FLASH_PROG PAGE = 0 .args : > FLASH_PROG PAGE = 0 /* Allocate IQ math areas: */ IQmath : > FLASH_PROG PAGE = 0 /* Math Code */ IQmathTables : > IQTABLES PAGE = 0, TYPE = NOLOAD //HWI and SWI runtime sections: RuntimeSection : > M01SARAM PAGE = 1 //SFRA Section: SFRA_IQ_Data : > L01SARAM, ALIGN = 64, PAGE = 1 //Control Sections: ControlVariables : > CPU_CLA_MSGRAM PAGE = 1 ReponseVariables : > CLA_CPU_MSGRAM PAGE = 1 CNTL_2P2Z_Coef : > CPU_CLA_MSGRAM PAGE = 1 CNTL_3P3Z_Coef : > CPU_CLA_MSGRAM PAGE = 1 CNTL_2P2Z_Var : > CLA_CPU_MSGRAM PAGE = 1 CNTL_3P3Z_Var : > CLA_CPU_MSGRAM PAGE = 1 ADCDRV_4ch_Section : > M01SARAM PAGE = 1 PWMDRV_NIFC_Section : > M01SARAM PAGE = 1 CNTL_3P3Z_Section : > M01SARAM PAGE = 1 CNTL_2P2Z_Section : > M01SARAM PAGE = 1 PWMDRV_1chHiResUpDwnCnt_Section : > M01SARAM PAGE = 1 //ISR-Functions: Net_terminals : > L01SARAM PAGE = 1 //SENSBus Stuff: SENS_Bus_Dev_Info : > L01SARAM PAGE = 1 SENS_Bus_Charger : > M01SARAM PAGE = 1 SENS_Bus_Charger_EE : > L01SARAM PAGE = 1 Charger_Alarms : > L01SARAM PAGE = 1 //Modbus Stuff: MODBUS_Lookup_Table : > M01SARAM PAGE = 1 //CAN_FIFO stuff: CAN_FIFO_buffer : > M01SARAM PAGE = 1 //Control Sections: FLASH_API_Section : > M01SARAM PAGE = 1 //Data Logger CrankAnalyzer : > L01SARAM PAGE = 1 //CLA section: //CLA_Prog : > L3SARAM PAGE = 1 Cla1Prog : LOAD = FLASH_CLA RUN = L3SARAM LOAD_START(_CLAfuncsLoadStart), LOAD_SIZE(_CLAfuncsLoadSize), LOAD_END(_CLAfuncsLoadEnd), RUN_START(_CLAfuncsRunStart) PAGE = 0 GROUP : LOAD = FLASH_CLA PAGE = 0, RUN = CLARAM1 PAGE = 1, LOAD_START(_CLATablesLoadStart), LOAD_SIZE(_CLATablesLoadSize), LOAD_END(_CLATablesLoadEnd), RUN_START(_CLATablesRunStart) { CLA1mathTables .const_cla } Cla1ToCpuMsgRAM : > CLA_CPU_MSGRAM PAGE = 1 CpuToCla1MsgRAM : > CPU_CLA_MSGRAM PAGE = 1 //Cla1DataRam0 : > CLARAM0, PAGE = 1 Cla1DataRam1 : > CLARAM1, PAGE = 1 CLAscratch : { *.obj(CLAscratch) . += CLA_SCRATCHPAD_SIZE; *.obj(CLAscratch_end) } > CLARAM1, PAGE = 1 /* * Uncomment the section below if calling the IQNexp() or IQexp() * functions from the IQMath.lib library in order to utilize the * relevant IQ Math table in Boot ROM (This saves space and Boot ROM * is 1 wait-state). If this section is not uncommented, IQmathTables2 * will be loaded into other memory (SARAM, Flash, etc.) and will take * up space, but 0 wait-state is possible. */ /* IQmathTables2 : > IQTABLES2 PAGE = 0, TYPE = NOLOAD { IQmath.lib (IQmathTablesRam) } */ /* * Uncomment the section below if calling the IQNasin() or IQasin() * functions from the IQMath.lib library in order to utilize the * relevant IQ Math table in Boot ROM (This saves space and Boot ROM * is 1 wait-state). If this section is not uncommented, IQmathTables2 * will be loaded into other memory (SARAM, Flash, etc.) and will take * up space, but 0 wait-state is possible. */ /* IQmathTables3 : > IQTABLES3 PAGE = 0, TYPE = NOLOAD { IQmath.lib (IQmathTablesRam) } */ }