ADDEQ R2,R4,R5		 	; If the Z flag is set make R2:=R4+R5
TEQS R4,#3 				; test R4 for equality with 3.
						; (The S is in fact redundant as the
						; assembler inserts it automatically.)
SUB R4,R5,R7,LSR R2 	; Logical right shift R7 by the number in
						; the bottom byte of R2, subtract result
						; from R5, and put the answer into R4.
MOV PC,R14 				; Return from subroutine.
MOVS PC,R14 			; Return from exception and restore CPSR
						; from SPSR_mode.