[9/29/2025, 1:35:43 PM] [INFO] Cortex_R5_0: GEL Output: Gel files loading Complete
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: OSPI (8S) - Octal Read Mode
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[9/29/2025, 1:35:45 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[9/29/2025, 1:45:08 PM] [ERROR] Cortex_R5_0: GEL: Error while executing OnTargetConnect(): Target failed to read 0x53208414 at (Read_MMR((0x53208000U+0x00000414U))!=0x4) [AM263Px_Periheral_Clocks.gel:467] at Program_RTI0_Clocks() [AM263Px.gel:192] at Configure_All_Peripheral_Clks() [AM263Px.gel:100] at OnTargetConnect()
[9/29/2025, 1:45:08 PM] [INFO] Cortex_R5_0: AM263Px
[9/29/2025, 1:45:08 PM] [INFO] Cortex_R5_0: Board Selected : CC
[9/29/2025, 1:45:08 PM] [INFO] Cortex_R5_0: Part Selected : Standard
[9/29/2025, 1:45:08 PM] [ERROR] Cortex_R5_0: Error: (Error -1170 @ 0x53208414) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 20.3.0.3656)
[9/29/2025, 1:45:08 PM] [ERROR] Cortex_R5_0: Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 20.3.0.3656)
[9/29/2025, 1:45:09 PM] [ERROR] Cortex_R5_0: Unable to determine target status after 20 attempts
[9/29/2025, 1:45:09 PM] [ERROR] Cortex_R5_0: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: OSPI (8S) - Octal Read Mode
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[9/29/2025, 1:45:16 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[9/29/2025, 1:45:17 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[9/29/2025, 1:45:42 PM] [ERROR] Cortex_R5_0: GEL: Error while executing OnTargetConnect(): Could not read 0x53208414: target is not connected at (Read_MMR((0x53208000U+0x00000414U))!=0x4) [AM263Px_Periheral_Clocks.gel:467] at Program_RTI0_Clocks() [AM263Px.gel:192] at Configure_All_Peripheral_Clks() [AM263Px.gel:100] at OnTargetConnect()
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: OSPI (8S) - Octal Read Mode
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RTI0 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RTI1 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RTI2 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RTI3 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: WDT0 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: WDT1 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: WDT2 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: WDT3 Clock Enabled (200MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN4_UART4 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: LIN5_UART5 Clock Enabled (160MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling OSPI Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (133MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling I2C Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling TRACE Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCAN2 Clock Enabled (80MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCAN3 Clock Enabled (80MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI4 Clock Enabled (48MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (400MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CPTS Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
[9/29/2025, 1:45:43 PM] [INFO] Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled***
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px Initialization Scripts Launched. Please Wait...
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Cryst_Clock_Loss_Status() Launched
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Crystal Clock present
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_SOP_Mode() Launched
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: SOP MODE = 0x00000003
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: OSPI (8S) - Octal Read Mode
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_Read_Device_Type() Launched
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: AM263Px_dual_or_lockstep_mode() Launched
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS0 DualCore Reset ***
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: *** R5FSS1 DualCore Reset ***
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5F ROM Eclipse
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_0 Released
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0_1 Released
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_0 Released
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1_1 Released
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: L2 Mem Init Complete
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MailBox Mem Init Complete
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: r5fss0 = 0x00000001
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: r5fss1 = 0x00000000
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS0 is in Dual-Core mode
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: R5FSS1 is in Dual-Core mode
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: CORE PLL Configuration Complete
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: CLK Programmed R5F=400MHz and SYS_CLK=200MHz
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Configure all Peripheral clocks()
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: *** Enabling Peripheral Clocks ***
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RTI0 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RTI1 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RTI2 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RTI3 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: WDT0 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: WDT1 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: WDT2 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: WDT3 Clock Enabled (200MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN0_UART0 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN1_UART1 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN2_UART2 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN3_UART3 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN4_UART4 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: LIN5_UART5 Clock Enabled (160MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling OSPI Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: OSPI0 Clock Enabled (133MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling I2C Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: I2C Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling TRACE Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Trace Clock Enabled (250MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCAN0 Clock Enabled (80MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCAN1 Clock Enabled (80MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCAN2 Clock Enabled (80MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCAN3 Clock Enabled (80MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MMCSD Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI0 Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI1 Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI2 Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI3 Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: MCSPI4 Clock Enabled (48MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: CONTROLSS Clock Enabled (400MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling CPTS Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: CPTS Clock Enabled (250MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RGMII5 Clock Enabled (5MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RGMII50 Clock Enabled (50MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: RGMII250 Clock Enabled (250MHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: TEMPSENSE Clock Enabled (32KHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: XTAL_MMC Clock Enabled (32KHz)
[9/29/2025, 1:45:44 PM] [INFO] Cortex_R5_0: GEL Output: ***All IP Clocks are Enabled***