FILE COMPARISON LOOP - linker - r5f_linker
Produced: 2/20/2025 4:14:18 PM

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Left file: C:\Users\a0233819\Documents\temp\linker.txt
Right file: C:\Users\a0233819\Documents\temp\r5f_linker.txt

1	#include "ti_enet_config.h"	<>	1	/----------------------------------------------------------------------------/
			2	/* r5f_linker.cmd */
			3	/* */
			4	/* (c) Texas Instruments 2020, All rights reserved. */
			5	/* */
2		=	6
3	/* This is the stack that is used by code running within main()	<>	7	/* USER CODE BEGIN (0) */
4	* In case of NORTOS,		8	/* USER CODE END */
5	* - This means all the code outside of ISR uses this stack		9	--retain="*(.intc_text)"
6	* In case of FreeRTOS		10	--retain="*(.irqStack)"
7	* - This means all the code until vTaskStartScheduler() is called in main()		11	--retain="*(.fiqStack)"
8	* uses this stack.		12	--retain="*(.abortStack)"
9	* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack		13	--retain="*(.undStack)"
10	*/		14	--retain="*(.svcStack)"
11	--stack_size=8192		15	--stack_size=0x2000
12	/* This is the heap size for malloc() API in NORTOS and FreeRTOS
13	* This is also the heap used by pvPortMalloc in FreeRTOS
14	*/
15	--heap_size=34000		16	--heap_size=0x1000
16	-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
17		=	17
18	/* This is the size of stack when R5 is in IRQ mode	<>	18	/* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
19	* In NORTOS,
20	* - Here interrupt nesting is disabled as of now
21	* - This is the stack used by ISRs registered as type IRQ
22	* In FreeRTOS,		19	-e_vectors
23	* - Here interrupt nesting is enabled
24	* - This is stack that is used initally when a IRQ is received
25	* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
26	* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
27	*/		20
			21	/* Stack Sizes for various modes */
28	__IRQ_STACK_SIZE = 256;	=	22	__IRQ_STACK_SIZE = 256;
29	/* This is the size of stack when R5 is in IRQ mode	+-
30	* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
31	*/
32	__FIQ_STACK_SIZE = 256;	=	23	__FIQ_STACK_SIZE = 256;
33	__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */	<>	24	__ABORT_STACK_SIZE = 256;
34	__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
35	__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */	=	25	__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
		-+	26	__SVC_STACK_SIZE = 4096;
36		=	27
		-+	28	/----------------------------------------------------------------------------/
			29	/* Linker Settings */
			30	/----------------------------------------------------------------------------/
			31	/* Memory Map */
37	SECTIONS	=	32	SECTIONS
38	{		33	{
39	/* This has the R5F entry point and vector table, this MUST be at 0x0 */		34	/* This has the R5F entry point and vector table, this MUST be at 0x0 */
40	.vectors:{} palign(8) > R5F_VECS		35	.vectors:{} palign(8) > R5F_VECS
41			36
42	/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000		37	/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
43	* i.e this cannot be placed in DDR		38	* i.e this cannot be placed in DDR
44	*/		39	*/
45	GROUP {		40	GROUP {
46	.text.hwi: palign(8)		41	.text.hwi: palign(8)
47	.text.cache: palign(8)		42	.text.cache: palign(8)
48	.text.mpu: palign(8)		43	.text.mpu: palign(8)
49	.text.boot: palign(8)		44	.text.boot: palign(8)
50	.text:abort: palign(8) /* this helps in loading symbols when using XIP mode */		45	.text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
51	} > MSS_L2		46	} > MSS_L2
52			47
53	/* This is rest of code. This can be placed in DDR if DDR is available and needed */		48	/* This is rest of code. This can be placed in DDR if DDR is available and needed */
54	GROUP {		49	GROUP {
55	.text: {} palign(8) /* This is where code resides */		50	.text: {} palign(8) /* This is where code resides */
56	.rodata: {} palign(8) /* This is where const's go */		51	.rodata: {} palign(8) /* This is where const's go */
57	} > MSS_L2		52	} > MSS_L2
58			53
59	/* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */		54	/* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
60	GROUP {		55	GROUP {
		<>	56
61	.data: {} palign(8) /* This is where initialized globals and static go */	=	57	.data: {} palign(8) /* This is where initialized globals and static go */
62	} > MSS_L2		58	} > MSS_L2
63			59
64	GROUP {	<>
65	.bss:.common:memp_memory_POOL_1792_base: (NOLOAD) {} palign(128)
66	.bss:.common:memp_memory_POOL_1024_base: (NOLOAD) {} palign(128)
67	.bss:.common:memp_memory_POOL_256_base: (NOLOAD) {} palign(128)
68	.bss:.common:memp_memory_POOL_512_base: (NOLOAD) {} palign(128)
69	.bss:.common:memp_memory_POOL_4096_base: (NOLOAD) {} palign(128)
70	.bss:.common:memp_memory_POOL_128_base: (NOLOAD) {} palign(128)
71	.bss:.common:memp_memory_PBUF_POOL_base: (NOLOAD) {} palign(128)
72	} > DSS_L3
73
74
75
76	/* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */	=	60	/* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
77	GROUP {		61	GROUP {
78	.bss: {} palign(8) /* This is where uninitialized globals go */		62	.bss: {} palign(8) /* This is where uninitialized globals go */
79	RUN_START(__BSS_START)		63	RUN_START(__BSS_START)
80	RUN_END(__BSS_END)		64	RUN_END(__BSS_END)
81	} > SBL_RESERVED_L2_RAM \| MSS_L2	<>	65	.sysmem: {} palign(8) /* This is where the malloc heap goes */
			66	.stack: {} palign(8) /* This is where the main() stack goes */
82			67	} > MSS_L2
83	.sysmem: {} palign(8) > SBL_RESERVED_L2_RAM \| MSS_L2 /* This is where the malloc heap goes */
84	.stack: {} palign(8) > SBL_RESERVED_L2_RAM \| MSS_L2 /* This is where the main() stack goes */
85		=	68
86	/* This is where the stacks for different R5F modes go */		69	/* This is where the stacks for different R5F modes go */
87	GROUP {		70	GROUP {
88	.irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)		71	.irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
89	RUN_START(__IRQ_STACK_START)		72	RUN_START(__IRQ_STACK_START)
90	RUN_END(__IRQ_STACK_END)		73	RUN_END(__IRQ_STACK_END)
91	.fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)		74	.fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
92	RUN_START(__FIQ_STACK_START)		75	RUN_START(__FIQ_STACK_START)
93	RUN_END(__FIQ_STACK_END)		76	RUN_END(__FIQ_STACK_END)
94	.svcstack: {. = . + __SVC_STACK_SIZE;} align(8)		77	.svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
95	RUN_START(__SVC_STACK_START)		78	RUN_START(__SVC_STACK_START)
96	RUN_END(__SVC_STACK_END)		79	RUN_END(__SVC_STACK_END)
97	.abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)		80	.abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
98	RUN_START(__ABORT_STACK_START)		81	RUN_START(__ABORT_STACK_START)
99	RUN_END(__ABORT_STACK_END)		82	RUN_END(__ABORT_STACK_END)
100	.undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)		83	.undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
101	RUN_START(__UNDEFINED_STACK_START)		84	RUN_START(__UNDEFINED_STACK_START)
102	RUN_END(__UNDEFINED_STACK_END)		85	RUN_END(__UNDEFINED_STACK_END)
103	} > SBL_RESERVED_L2_RAM \| MSS_L2	<>
104
105	/* Sections needed for C++ projects */
106	GROUP {
107	.ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
108	.init_array: {} palign(8) /* Contains function pointers called before main */
109	.fini_array: {} palign(8) /* Contains function pointers called after main */
110	} > MSS_L2	=	86	} > MSS_L2
111			87
112	/* any data buffer needed to be put in L3 can be assigned this section name */		88	/* any data buffer needed to be put in L3 can be assigned this section name */
113	.bss.dss_l3 {} > DSS_L3		89	.bss.dss_l3 {} > DSS_L3
114			90
115	/* For NDK packet memory*/	<>	91	/* this is used only when IPC RPMessage is enabled, else this is not used */
116	.bss:ENET_CPPI_DESC (NOLOAD) {} ALIGN (128) > CPPI_DESC		92	.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
117
118	.enet_dma_mem {
119	#if (ENET_SYSCFG_PKT_POOL_ENABLE == 1)
120	(ENET_DMA_PKT_MEMPOOL)
121	#endif
122	} (NOLOAD) {} ALIGN (128) > DSS_L3
123	.bss:UDP_IPERF_SND_BUF (NOLOAD) {} ALIGN (128) > DSS_L3
124	}	=	93	}
125			94
		-+	95	/----------------------------------------------------------------------------/
126	MEMORY	=	96	MEMORY
127	{		97	{
128	R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040		98	R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
129	R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00003FC0		99	R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00003FC0
130	R5F_TCMB : ORIGIN = 0x00080000 , LENGTH = 0x00004000		100	R5F_TCMB : ORIGIN = 0x00080000 , LENGTH = 0x00004000
131	SBL_RESERVED_L2_RAM (RW) : origin=0x10200000 length=(0x00020000 - 0x00004000)	+-
132		=	101
133		<>
134	/* CPPI descriptor memory */
135	CPPI_DESC : ORIGIN = (0x10220000 - 0x00004000), LENGTH = 0x00004000
136
137	/* when using multi-core application's i.e more than one R5F active, make sure	=	102	/* when using multi-core application's i.e more than one R5F active, make sure
138	* this memory does not overlap with other R5F's		103	* this memory does not overlap with other R5F's
139	*/		104	*/
		<>	105	SBL_RESERVED_L2_RAM (RW) : origin=0x10200000 length=0x00020000
			106
140	MSS_L2 : ORIGIN = 0x10220000 , LENGTH = 0x000D0000		107	MSS_L2 : ORIGIN = 0x10220000 , LENGTH = 0x000C8000
141		=	108
142	/* This is typically used to hold data IO buffers from accelerators like CSI, HWA, DSP */		109	/* This is typically used to hold data IO buffers from accelerators like CSI, HWA, DSP */
143	DSS_L3: ORIGIN = 0x88000000, LENGTH = 0x00390000		110	DSS_L3: ORIGIN = 0x88000000, LENGTH = 0x00390000
		<>	111
			112	HWA_RAM (RW) : origin=0x82000000 length=0x00020000
			113
			114	/* MSS mailbox memory is used as shared memory, we dont use bottom 326 bytes, since its used as SW queue by ipc_notify /
			115	RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0xC5000000, LENGTH = 0x1F40
144	}	=	116	}
		<>	117	/----------------------------------------------------------------------------/
			118