void uDMAInit()
{
   uDMAEnable();
   uDMAControlBaseSet(uDMAControlTable);

   /* Ensure channel is disabled before modifying register. */
   uDMAChannelDisable(UDMA_CH24_ADC1_0);
   uDMAChannelAssign(UDMA_CH24_ADC1_0);
   uDMAChannelAttributeDisable(UDMA_CH24_ADC1_0, UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK);
   uDMAChannelScatterGatherSet(UDMA_CH24_ADC1_0, MAX_ADC_SAMPLES, (void*)TaskList, true);

   uDMAChannelEnable(UDMA_CH24_ADC1_0);
}

void ADC1SS0uDMATransferFinishedISR()
{
   ADCIntClear(ADC1_BASE, 0);
   if (uDMAIntStatus() & (1 << (UDMA_CH24_ADC1_0 & 0x1F)))
   {
      GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_5, 0);
      GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_5, GPIO_PIN_5);
   }
}

void ADCInit()
{
   ADCSequenceConfigure(ADC1_BASE, 0, ADC_TRIGGER_ALWAYS, 1);
   ADCSequenceStepConfigure(ADC1_BASE, 0, 0, ADC_CTL_CH1); //UZELL_A
   ADCSequenceStepConfigure(ADC1_BASE, 0, 1, ADC_CTL_CH4); //UZELL_B
   ADCSequenceStepConfigure(ADC1_BASE, 0, 2, ADC_CTL_CH5); //UZELL_C
   ADCSequenceStepConfigure(ADC1_BASE, 0, 3, ADC_CTL_CH6); //UZELL_D
   ADCSequenceStepConfigure(ADC1_BASE, 0, 4, ADC_CTL_CH7); //UZELL_E
   ADCSequenceStepConfigure(ADC1_BASE, 0, 5, ADC_CTL_CH2); //UZELL_F
   ADCSequenceStepConfigure(ADC1_BASE, 0, 6, ADC_CTL_CH0); //UZELL_1
   ADCSequenceStepConfigure(ADC1_BASE, 0, 7, ADC_CTL_IE | ADC_CTL_END | ADC_CTL_CH8); //USTACK

   ADCReferenceSet(ADC1_BASE, ADC_REF_INT);

   ADCIntRegister(ADC1_BASE, 0, ADC1SS0uDMATransferFinishedISR);

   ADCIntEnableEx(ADC1_BASE, ADC_INT_DMA_SS0);

   ADCSequenceEnable(ADC1_BASE, 0);
}