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CC1120: Synchronous serial mode BER/PER test

cc1120user
Prodigy 100 points
Part Number: CC1120


Hello,

Question on performing bit/packet error rate tests on the cc1120. We are trying perform a BER test while the cc1120 is on our product using the synchronous serial rx mode. We want to evaluate if there is any sensitivity degradation when the cc1120 is on our product.

While we are able to successfully retrieve our packets, we are also getting garbage data in between the transmission of the packets. In other words, the cc1120 continues to output data even if there is no packet and only noise coming in. I would have expected the cc1120 to know when the end of the packet was and to stop outputting data at that point.

My questions are:

  • Are we supposed to receive garbage data in between packet transmissions while operating in sychronous serial mode?
    • If yes, is the idea here to use a signal such as PKT_SYNC_RXTX to 'mask' the data (or as data valid signal) to alert the software that this is a valid packet?

  • Is synchronous serial mode the best mode to achieve a BER test?
  • Is synchronous serial mode identical to FIFO mode except for the fact that the data is being output on GPIO pins?

  • 0
    Prodigy 22 points

    I'm also experiencing this same issue.

  • 0
    TI__Guru**** 317180 points

    I would recommend using FIFO mode (send/ receive packets) and calculate BER based on PER from the equations given in: https://en.wikipedia.org/wiki/Bit_error_rate

    cc1120user said:
    Is synchronous serial mode identical to FIFO mode except for the fact that the data is being output on GPIO pins

    Yes. But the toggling of the GPIOs could cause a loss in sensitivity.  

  • 0 in reply to TER
    Prodigy 100 points

    Thank you TER.

    Does synchronous serial mode also perform de-whitening and error correction on the data?

  • 0 in reply to TER
    Prodigy 100 points

    TER, does reading the FIFO buffer through SPI also cause a degradation of sensitivity?

  • 0 in reply to cc1120user
    TI__Guru**** 317180 points

    No, since you typically read of the packet over SPI after it has been received. 

  • 0 in reply to TER
    Prodigy 100 points

    Thanks TER,

    Would also like to know if synchronous serial mode also performs de-whitening and error correction on the data?

  • 0 in reply to cc1120user
    TI__Guru**** 317180 points

    De-whitening, yes I believe so. What do you define as error correction in this context? 

  • 0 in reply to TER
    Prodigy 100 points

    I just mean the standard crc packet discarding that should occur if an error is detected.

    Is the PKT_SYNC_RXTX signal supposed to work in synchronous serial rx mode? This signal does not seem to assert as described in the datasheet. 

  • 0 in reply to cc1120user
    TI__Guru**** 317180 points

    I have to verify this but I don't have a logic analyzer with me at the moment meaning that I have to look at it next week. 

    But: Do you use sync. serial mode in the application or is it just for performance testing? If the latter, why use this mode when FIFO mode gives better performance? 

  • 0 in reply to TER
    Prodigy 100 points

    My goal is to have a BER/sensitivity test for our product. We use FIFO mode in our application.

    Originally I was under the impression that FIFO mode and synchronous serial mode performance were similar due to the wording of 5.1.2.1 in the cc1120 userguide. It says: 

    "Synchronous serial mode makes use of the WaveMatch detector, which means the performance will be similar to the performance in FIFO mode"

    Of course, you clarified that the GPIO toggling may cause a degradation in performance. 

    To answer your question 'why not use FIFO mode': Perhaps you are right and this is the solution we should have pursued in the beginning.

    Initially when we started this, the only pins where we had good external connections (on our board) were the GPIO pins, so it seemed like a good choice to use sync serial mode given that it uses the GPIO pins to output the data and the performance is similar to FIFO.

    I was also concerned that because the FIFO buffer only stores the payload and not the preamble or sync word, I thought I could get a more accurate (than an estimate from packet error rate)  BER number if I could read what preamble and sync word the chip was recovering. That is why I also asked if in sync mode packets are dropped due to crc filtering. 

    Let me know what you think.

  • 0 in reply to cc1120user
    TI__Guru**** 317180 points

    - Preamble and sync is not required for a PER/ BER test and not relevant. The preamble and sync word received is not stored by the chip. 

    - If you use the FIFO in your application you should use this for PER testing to ensure that you test with the same setup in both cases. Use the same payload length in both cases.