https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1682441/sn65dsi84-q1-sn65dsi-shows-test-pattern-does-not-pass-through-mipi-dsi-data/6483968Tue, 15 Sep 2026 15:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:45c26847-fd8b-4aca-9c01-aa8f99dc9ee9Sam SchHere is the SN65DSI register dump:https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1682443/tps7a53evm-031-tps7a53evm-031-gerberTue, 15 Sep 2026 15:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e23d9534-c8bb-4161-bac1-147ea2f0669aJoe RoseberryPart Number: TPS7A53EVM-031 Hello: Please send Gerber for TPS7A53EVM-031. Thanks, JoeTPS7A53EVM-031Datacom modulehttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1680959/ccstudio-ccs-v3-x-cgt-4-10/6483967Tue, 15 Sep 2026 15:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:acf7cd92-b98a-47b2-aad7-0b2d02d964d3KiInsung, [quote userid="128600" url="~/support/processors-group/processors/f/processors-forum/1680959/ccstudio-ccs-v3-x-cgt-4-10"]that includes CGT 4.1.0. I believe it is likely version 3.1?[/quote] That is correct. You need CCS 3.1. Please start a private E2E conversation to discuss further. Thanks kihttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1682441/sn65dsi84-q1-sn65dsi-shows-test-pattern-does-not-pass-through-mipi-dsi-dataTue, 15 Sep 2026 15:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8bdec0bb-b6ff-4a1f-9a22-1175a3869eb6Sam SchPart Number: SN65DSI84-Q1 Hello at TI, We are working with the SN65DSI for a display in an HMI application. The DSI Tuner tool has been used to aid setting up the SN65DSI registers with values from the LCD's driver IC EK79001. Hardware: -1024*600, 7" display -SN65 LVDS output lanes are 'swapped' on channel A -Raspberry pi Compute Module 4 is the DSI source -length-matching and high-speed differential layout techniques were designed into the pcb -10cm flat flex cable between the SN65DSI board and the raspberry pi module The test pattern shows up, but no DSI graphics data appears on the screen and there is a gray "arc" in each corner of the screen. Sometimes the PLL error bit is set. Any help on this issue is greatly appreciated! Thanks and God bless.Infotainment & ClusterSN65DSI84-Q1https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1681741/txs0108e-q1-a-question-about-level-shifter-channel-waveform/6483957Tue, 15 Sep 2026 14:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:eba76d41-0f98-4155-abba-2ba1f26bd57cTyler TownsendHi Ivan, The TXS0108E-Q1 is a passive level shifter. What is the state of the OE pin when you expect CS to be logic low? Regards, Tylerhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1680704/am6442-atomicity-of-ordinary-accesses-to-ddr-msram-and-r5f-tcm/6483951Tue, 15 Sep 2026 14:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6d8b79fd-45ca-4187-8ff8-4182e6473cfaAnastas YordanovHello Hiroki Hoshina-san, Please find attached the first 3 answers as aligned with the expert: [quote userid="649787" url="~/support/processors-group/processors/f/processors-forum/1680704/am6442-atomicity-of-ordinary-accesses-to-ddr-msram-and-r5f-tcm"] I have a related question about ordinary aligned accesses such as LDR and STR , not exclusive accesses such as LDREX and STREX . If one core writes and another core reads the same physical memory location at approximately the same time, could you please clarify the following for DDR, MSRAM, and R5F TCM? [/quote] Q1. [quote userid="649787" url="~/support/processors-group/processors/f/processors-forum/1680704/am6442-atomicity-of-ordinary-accesses-to-ddr-msram-and-r5f-tcm"]What is the largest naturally aligned access size guaranteed to be single-copy atomic between cores: 8, 16, 32, or 64 bits?[/quote] A1: Largest naturally aligned access size guaranteed single‑copy atomic between cores: Core Guaranteed atomic size (Architectural) Cortex‑R5F (ARMv7‑R, AArch32) 32 ‑bit (word) . LDRD/STRD (64‑bit) are not guaranteed atomic as a whole — architecturally they are treated as two separate 32‑bit accesses. Cortex‑A53 in AArch32 32 ‑bit (same as above). Cortex‑A53 in AArch64 Up to 64‑bit (doubleword) for naturally aligned LDR/STR Xn, within the coherent/shareable domain, the interconnect actually supports. So: 32 bits is the size guaranteed by the architecture across all three core types when at least one side is a 32‑bit core (R5F). If both initiators are AArch64 A53 cores and the memory/interconnect path supports it, 64‑bit can also be atomic — but that is not guaranteed once an R5F (32 ‑ bit only) is one of the observers , and TI does not publish a blanket 64‑bit cross‑initiator atomicity guarantee for DDR/MSRAM/TCM. AM64x TRM describes bus/interconnect widths and arbitration behavior, but I could not find an explicit "single ‑ copy atomicity" statement present in the AM64x TRM for the DDR, MSRAM, or TCM at the SoC‑interconnect level. The “single-copy atomicity” guarantee is fundamentally defined by the ARM Architecture Reference Manual , and it holds at the SoC level only to the extent that TI's interconnect (VBUSM/AXI, bridges, memory controllers) preserves each CPU‑side transaction as a single indivisible transfer to the target memory. Reference source for R5F: ARM Architecture Reference Manual for ARMv7-R, Cortex-R5F (DDI0406C_d_armv7ar_arm.pdf) / Section, Memory Model and Section , Atomicity in the ARM Architecture / Single-copy atomicity The ARMv7 architecture specifies that single-copy atomicity is guaranteed for aligned accesses up to the size of the native word (32-bit for the ARMv7-R Cortex-R5F). Reference source for the A53: ARM Architecture Reference Manual for ARMv8-A, Cortex-A53 (DDI0487M_c_a-profile_architecture_reference_manual.pdf) : Section, "AArch64" under Section, "Memory Model." In AArch64, the architecture expands the guarantee for naturally aligned accesses to 64-bit (Doubleword), provided the implementation (the interconnect) supports it. The "Weakest Link" Rule: This is an architectural implication. If an R5F (observing via AXI/VBUSM) is part of the shareability domain, the system must respect the requirements of the most restrictive observer to maintain architectural correctness. Q2. [quote userid="649787" url="~/support/processors-group/processors/f/processors-forum/1680704/am6442-atomicity-of-ordinary-accesses-to-ddr-msram-and-r5f-tcm"]For a naturally aligned 32-bit access, is the reader guaranteed to observe either the complete old value or the complete new value, without observing a mixture of both?[/quote] A2: For a naturally aligned 32‑bit LDR/STR: another observer will never see a torn/mixed value, only the fully‑old or fully‑new 32‑bit pattern. This applies for DDR, MSRAM, and R5F TCM as long as: the access is naturally aligned (word‑aligned address), the memory region is a supported type (Normal or Device, non‑exclusive access as you specified), and the interconnect delivers the 32‑bit transaction as a single transfer to the memory (which is the normal case for word‑sized CPU accesses on TI's VBUSM/AXI fabrics - none of the TRM material found indicates 32‑bit CPU words get split by TI's interconnect). Q3. [quote userid="649787" url="~/support/processors-group/processors/f/processors-forum/1680704/am6442-atomicity-of-ordinary-accesses-to-ddr-msram-and-r5f-tcm"]If one naturally aligned 32-bit CPU access is internally divided into multiple physical data transfers, can another initiator’s access to the same location be serviced between those transfers? If so, is it still guaranteed that the intermediate value cannot be observed?[/quote] A3: By architecture and by design, a naturally aligned 32‑bit access is not split into multiple physical bus transfers on any of these paths — it is issued and completed as one transfer at the width of the target bus (VBUSM/AXI data widths at the R5FSS main memory interface and TCM target interface are 64‑bit, DDR/MSRAM controllers accept ≤ their native width in a single beat). Because it isn't split, there is no intermediate/partial state for another initiator to observe, and no interleaving hazard at the 32‑bit granularity. This only becomes a real risk for accesses wider than a single naturally aligned atomic unit — e.g., an unaligned 32 ‑ bit access, or a 64 ‑ bit LDRD/STRD/LDP/STP, which architecturally are not atomic as a whole and could, depending on the interconnect, be serviced with another initiator's transaction interleaved between the two halves . In that case the intermediate (half old/half new) value can be observed by another initiator. The AM64x TRM does not claim otherwise for LDRD/STRD‑sized or larger accesses. Please expect the follow-up on your Q4 and Q5 as soon as the remaining answers are confirmed. Thanks Best Regards, Anastas Yordanovhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1682193/lm51581-negative-to-positive-dcdc-converter/6483954Tue, 15 Sep 2026 14:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fe3a8eb9-9f5d-4ec6-9125-43eb55d33a43Hassan JamalHi Shunsuke, Yes, LM51581 can be considered for a –48 V to +5 V / 1 A application using a negative-input-to-positive-output buck-boost configuration. In this topology, the IC is referenced to the negative input rail, while the output is regulated positive with respect to system ground. TI application note SNVA740, “Negative Input to Positive Output made SIMPLE”, is a good reference for understanding the topology and the required feedback level shifting. https://www.ti.com/lit/an/snva740/snva740.pdf?ts=1789480783184&ref_url=https%253A%252F%252Fwww.google.com%252F For –48 V input and +5 V output, the switch-node voltage stress is approximately |VIN| + VOUT ≈ 53 V, so the complete input range and possible input transients should be checked against the LM51581 ratings. Also, the required duty cycle is relatively low, so the switching frequency should be selected carefully considering the device minimum on-time. The inductor, diode, feedback network, compensation and voltage ratings would then need to be designed based on the actual VIN range and 5 V / 1 A requirement. Best regards, Hassanhttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1681422/am263p4-am263px-does-autosar-mcal-make-sil-2-development-easier-and-more-manageable-vs-native-mcu-sdk-sdl/6483950Tue, 15 Sep 2026 14:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c4477523-6dce-451d-8466-3480f662b5deRyan DavittHey Mustafa, Sorry for the delay here. I am still working on confirming an answer for question 1. For question 2, the AUTOSAR MCAL that we provide will be ASIL-D certified with the upcoming 26.01.00 LTS release. There is also an previous version (09.01) that is ASIL-D certified as well. With each certified release, coverage, traceability reports, and safety manuals will be made available through secure resource downloads on TI.com. MISRA reports are always available with AUTOSAR MCAL releases. I will follow up with an answer to question 1 later this week. Best, Ryanhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1682424/bq25672-bq25672-charger-ic-vsys-and-vbat-voltage-issue/6483942Tue, 15 Sep 2026 14:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8a386383-fce5-49dc-b6b7-97b70d1f2feaJeff FHi Syam, V(SYS) is the higher of MINSYS (or SYSMIN) voltage (defaults to 3.6V for 1S application) or the battery voltage plus up to 600mV after termination. MINSYS register cannot be set higher than battery regulation voltage VREG register. If you didn't change the MINSYS voltage register to 4.0V, I can't explain how VSYS is 4V. What do the status and fault registers in REG0x1B through 0x27 report? Regards, Jeffhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1681673/j722sxh01evm-can-am67a-usb30-port-support-gadget/6483933Tue, 15 Sep 2026 14:48:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:41635b04-1464-46a3-89a7-b01791abd980Gang Hua[quote userid="542150" url="~/support/processors-group/processors/f/processors-forum/1681673/j722sxh01evm-can-am67a-usb30-port-support-gadget/6483290"]I'm asking whether the MIPI camera video can be output through the AM67A USB3.0 port using the UVC protocol.[/quote] I am not sure if I understand you correctly. Do you mean that AM67A receives MIPI camera raw video, process it with VPAC, and then output YUV video through USB3.0 port using the UVC protocol?https://e2e.ti.com/support/sensors-group/sensors/f/sensors-forum/1682132/iwrl6432w-how-to-support-wcsp-gpio-configuration-in-sysconfig-and-mmwave-l-sdk/6483932Tue, 15 Sep 2026 14:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a0755735-316e-4440-a2f1-15eeafeb20c2David CassityHi James, Thank you for bringing this to our attention. I have notified the relevant parties to fix this problem. For now, your customer will have to use a different pin. Best, Davidhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1679991/sn74hcs595-q1-abnormal-output-low-level/6483929Tue, 15 Sep 2026 14:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:19a1c6b7-dc4e-48c8-8303-e96a713b2fb5Frank QINLooking forward for feedback.https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1682435/tlk10232evm-tlk10232evm-tlk10232-ibert-test-failure-no-sync-between-evm-and-systemTue, 15 Sep 2026 14:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fd524647-c336-47ac-b036-25f83fa7c4b4Dror LaorPart Number: TLK10232EVM Other Parts Discussed in Thread: TLK10232 , TEST2 We are seeking your support with an unresolved issue using the TLK10232. Summary: Setup: TLK10232 EVM connected to our FPGA-based tester board via optical link Test1 (EVM loopback) – PASS Test2 (EVM + system traffic) – PASS Test3 (IBERT / PRBS on both sides) – FAIL (no synchronization) Details: PRBS31 generated and verified on both sides AN and LT disabled SYNC_STATUS_CHECK_DISABLE set Multiple TX/RX equalization settings tested (no impact) Configuration script attached (same used for working tests) Observation: When connecting the EVM to our system for IBERT, there is no sync/lock indication, although both sides work independently. We would appreciate your guidance on: Required configuration for IBERT interoperability between EVM and external FPGA Any known limitations or required alignment (clocking, polarity, training, etc.) Review of our configuration for potential mismatches This issue is currently blocking our progress. See attached correspondace and locked discussion here: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1650809/tlk10232evm-tlk10232-ibert-test-failure-no-sync-between-evm-and-systemTLK10232Datacom moduleTLK10232EVMTest2https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1679951/msp430f67641a-msp430f67641a-three-phase-meter-resets-on-load-insertion/6483922Tue, 15 Sep 2026 14:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0b707cac-1a94-4272-aac4-3867aac105bcMassimo RomanoNew event: It has frozen in the middle of a cycle (board led was enabled), but WDT didn't reset the circuit after time elapsed. I expected WTD to reset the MCU eventually. WDTCTL = WDTPW | WDTSSEL__VLO | WDTIS__512K; // WDT , VLOCLK (~10kHz) SFRRPCR = SYSRSTRE | SYSRSTUP | SYSNMI; //rest is NMI SetVCore (PMMCOREV_3); //routine that set PMMCOREV at level 3 step by step) //clock config UCSCTL3 = SELREF__REFOCLK; // FLLRef = internal REFOCLK (~32.768kHz) UCSCTL4 = SELA__REFOCLK | SELS__DCOCLKDIV | SELM__DCOCLK; // ACLK = REFOCLK, SMCLK = DCO/n, MCLK = DCO __bis_SR_register (SCG0); UCSCTL0 = 0x0000 ; UCSCTL1 = DCORSEL_6; UCSCTL2 = FLLD__1 | 600 ; __bic_SR_register (SCG0);https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1682393/dslvds1047-1048evm-dimensions-dslvds1047-1048evm/6483919Tue, 15 Sep 2026 14:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:70220655-69bf-49e6-b086-d55cc2ed0b99Brandon Fisher94Hi Bill, Welcome to the E2E forums. The board is 2800mils by 2700 mils, see the below image for the orientation. However there are no mounting holes on this EVM. Best Regards, Brandon Fisherhttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1676107/msp430g2553-interfacing-msp-gang-programmer-with-a-raspberry-pi/6483918Tue, 15 Sep 2026 14:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:865164d3-07ed-4ea3-862d-18f961f9e97eBrian LeeHi Kartik, Sorry for the delayed response, I was out of office. Additionally, I think for this issue it would be best to contact Elprotronic's support directly. I can provide additional support for how to use the MSP-GANG with our MSP devices, but our team does not have the expertise for interfacing with the programmer outside of the GUI and DLL. Elprotronic's Contact information: Support email - info@elprotronic.com Official Website - Elprotronic Inc. | Provider of Flash and Gang Programmers Best Regards, Brianhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1677775/lp-am243-lp-am243-usb-debug-mcu-and-firmware/6483917Tue, 15 Sep 2026 14:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3a158487-25ca-4a6b-a4a5-2e1e161b4a6bBayu EkoOkay, thank you very much. I will use LP-XDS110 for my custom board AM243xhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1680684/lmr51635-lmr51635-design/6483915Tue, 15 Sep 2026 14:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:94a9b8da-3567-4420-95c2-5cce511a2f88Tania LazaroThe signals for the SW and the BST arehttps://e2e.ti.com/support/sensors-group/sensors/f/sensors-forum/1682433/iwrl6432aop-farfield-source-fileTue, 15 Sep 2026 14:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7e07030a-6bcc-484b-ae0c-f36ad551b35csoufien MenaiPart Number: IWRL6432AOP Hello, is there a possibility to get the simulated farfield of the 5 antenna's in order for me to simulate them with my EM software (CST µwave studio) , because I would like to simulate the IWR6432AOP with the presence of a front cover and determine the appropriate shape of the front cover? I would like also to make the simulation @ differente frequency inside the bandwith . Thanks in advance.Industrial AutomationIWRL6432AOPhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1679402/ccstudio-alternate-communication-in-ccxml-required-for-am2612-real-time-debug/6483912Tue, 15 Sep 2026 14:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7659db04-5bae-4a8c-ab32-d30cb26cb72bKiHi Ted, I assume you are referring to the UART Connection type. While that interface to add it from the "Basic" tab of the ccxml file is missing, you can manually add it from the "Advanced" tab as a "New Connection". However, there is a known limitation where you can only select devices to add to it and not cpus. Hence you will not be able to set up the connection as mentioned in the document you referenced. We plan on fixing this in the upcoming CCS 21.1.0 release: https://sir.ext.ti.com/jira/browse/EXT_EP-12906 Thanks ki