https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1655125/tps25751-sink-only-battery-charger-application-with-tps25751-and-bq25792Sun, 14 Jun 2026 00:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:33b992f5-80aa-441d-9b1e-75fb409dca1bIlham BuhariePart Number: TPS25751 Other Parts Discussed in Thread: BQ25792 , Hello, Looking for some help with troubleshooting my deisgn that includes TPS25751 as the PD controller and BQ25792 as the battery charger. The TPS, BQ and an EEPROM share an I2C bus. The MCU on the board has a direct I2C to the TPS. Please see attached schematics. Please note the VIN_3V3 on the TPS is connected to the 3.3V rail with a board rework (it was a miss on my part during the schematic phase) I used the TI tool to create a configuration (JSON settings pasted below) that was flashed successfully using the aardvark header. My test setup Macbook 96W charger at the PD input. Battery input uses a bench supply set at 14.7V current limit to 250mA What is Working? The TPS negotiates the correct voltages (5V, 9V, 15V and 20V) depending on the charger input. The BQ accepts the 14.7V input and turns on Vsys i.e. all my downstream voltage rails are good. What is NOT Working? The TPS does not enable PPHV so the BQ never receives power from the TPS. Appreciate any guidance with this. { "questionnaire": { "device": "TPS25751", "toolBuildVersion": "2.0.0", "answers": [ null, 4, 4, 3, 1, 0, 3, 0, 1, 1, 1, 0, 0, 0, 16.8, 0.25, 0.04, 0.04 ], "vendorId": "0000", "productId": "0000", "version": "1.0.0.2" }, "configuration": { "data": { "selected_ace": [ { "register": 6, "data": [ 0, 0, 0, 0, 0, 0, 0, 0 ] }, { "register": 22, "data": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3 ] }, { "register": 40, "data": [ 0, 0, 46, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 ] }, { "register": 41, "data": [ 50, 80, 129, 0, 0 ] }, { "register": 50, "data": [ 5, 170, 42, 44, 145, 1, 32, 44, 209, 2, 0, 44, 177, 4, 0, 244, 65, 6, 0, 244, 177, 4, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] }, { "register": 51, "data": [ 4, 100, 144, 1, 16, 44, 177, 4, 25, 44, 65, 6, 0, 44, 209, 2, 153, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] }, { "register": 55, "data": [ 59, 192, 18, 65, 144, 145, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] }, { "register": 66, "data": [ 26, 0, 8, 0 ] }, { "register": 92, "data": [ 14, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] }, { "register": 112, "data": [ 3 ] }, { "register": 119, "data": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 127, 0 ] }, { "register": 120, "data": [ 0, 0, 0, 128, 0, 0, 0, 128, 0 ] }, { "register": 122, "data": [ 0, 0, 0, 0 ] }, { "register": 123, "data": [ 0, 2, 255, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] }, { "register": 125, "data": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] }, { "register": 126, "data": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] }, { "register": 152, "data": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] } ] } } }TPS25751BQ25792Wearables (non-medical)https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1655124/tps6594-q1-rstout_l-keeps-lowSat, 13 Jun 2026 21:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:46a381e5-a0f0-4268-a0ec-8c5cd6a9e661Max Chen1Part Number: TPS6594-Q1 we use TPS6594141BRWERQ1 and LP876441B1RQKRQ1 with SoC XJ7200GALM we had a problem from beginning, which is RSTOUT_L keeps Low on some boards, so this will keep SoC no boot, and system current very low. this issue can go away by cycling the system power on some boards. but some boards remain this issue, no recovery, PMIC no power rails output. we also tried to debug with TI EVM bard, but it never succeeded to access my target board via EVM, TI supporter did not give good instructions for this either, now we are sitting on terrible situation to move the develoment to next phase, I am seeking for TI's PMIC expert support on: Topic1: what causes RSTOUT_L and system no boot? Topic2: how can we ultilize EVM to debug traget board PMICs even when target board SoC does not boot?Advanced Driver Assistance Systems (ADAS)TPS6594-Q1https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1651618/tida-010979-bring-up-software-development-environment-problems/6381787Sat, 13 Jun 2026 17:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:69a3f6d2-f94e-4c23-a29a-0bbcc3cb93f7Robert HuangHi Masoud, A big difference is that Han doesn't proceed Readme.txt under 'EtherCAT Beckhoff CiA402 Beckhoff Demo Patch' folder where the steps Han has not done are TI_ESC_CiA402_application_modifications.patch (step 3) and Rebuild EtherCAT Firmware HAL Libraries(step 4). Please help double check they are not necessary to do. I'll also try it again without these two steps next week. BR, Robert Huanghttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1653763/bq78350-r1a-system-side-fuel-gauges-for-multi-cell-packs/6381780Sat, 13 Jun 2026 16:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e0757c04-78b3-43fd-9928-2263cb8240c8Tim HennesyOk I can have it wait 2 seconds before engaging the fets to be sure it has had a full measurement period. I'm gonna try it and see how this works out, thanks for talking through this with me.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1654685/tps62932-verification-of-tps62932-enable-en-pin-control-scheme/6381779Sat, 13 Jun 2026 16:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9ada1dcd-d69e-4bca-a1f7-55be1eeb4d74Bala Aravind MYour quick support is highly appreciated.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1655120/ucc256403-dc-dc-buck-convert-er-selectionSat, 13 Jun 2026 16:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b6de86b6-c793-4f6f-8247-06d16da35bc5Avijeet MondalPart Number: UCC256403 I am looking for the Low noise Buck converter non isolated Input voltage : 40V ~ 80V ouput voltage : 12V Ouptut current : 25 ~30A non isolated supplyUCC256403https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1655119/ads127l14-tem-project-schematic-validationSat, 13 Jun 2026 16:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8ac63c85-80e3-4937-9eb4-1fbae369b14fAvijeet MondalPart Number: ADS127L14 Request Project Document TI_Verification_Request.docx Schematic of the section RX_Board_Rev_01.pdf We request you to please review the schematic and its connection We kindly request Texas Instruments Application Engineering to review the above configuration in detail and confirm or correct each of the 10 verification questions listed in Section 6. Any errors or recommended changes identified at this stage will be incorporated before PCB fabrication is initiated, preventing costly board respins. We are happy to provide the complete schematic, full ADS127L14 pin connection table, and REF5025 connection details if required for a more thorough review. Thank you for your support. Is the ground isolation strategy (Rx board AGND/DGND isolated from FPGA GND via ISO7762DW) correct and sufficient for this application? Is 15 FPGA GPIO pins sufficient to communicate with all 5 ADS127L14 ADCs in 1-lane Star TDM mode using the described signal sharing strategy? Can DCLK and FSYNC from Board 1 be used as the timing reference for all 5 boards given that all boards share the same CLKIN source and START signal? Is wired-OR of all 5 ERROR pins (open-drain) correct, and is ERR_FLAG in STATUS_DP header sufficient to identify the faulty board without individual CS lines? Is the primary proxy SDO approach (only Board 1 SDO connected, boards 2-5 SDO tied to 10k to DGND) correct given shared CS? Are the U1 and U2 isolator pin connections and side assignments (U1: ADC=Side1, FPGA=Side2; U2: FPGA=Side1, ADC=Side2) correct per ISO7762DW datasheet Figure 4-3? Is GPIO0/TDM (pin 3) direct tie to DGND (no resistor) the correct method to select 1-lane Star TDM given the 25k internal driver and 3k maximum external resistor constraint? Is GPIO1/HDR (pin 4) direct tie to IOVDD (no resistor) correct to permanently enable STATUS_DP header byte for ERR_FLAG identification? Are bypass capacitor values (AVDD1/AVDD2: 2.2uF to AVSS, CAPA: 10uF to AVSS, CAPD: 2.2uF to DGND, IOVDD: 2.2uF to DGND) correct per ADS127L14 datasheet Table 9-3? Is REF5025AIDR with GND pin tied to AVSS (-2.5V) and VIN tied to AVDD1 (+2.5V) the correct configuration to generate VREF = 2.5V for bipolar ±2.5V input range?Industrial AutomationADS127L14https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1653035/tps25981-parallel-application/6381778Sat, 13 Jun 2026 16:05:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9bd01085-70b4-40ab-b22e-09c58d9262ceMani RayHello Jeff, Sorry for the delay response. One device will turn on first because of the process variations ,during start up that turned on device provides most of the c out current & load current it will hit ilim & later TSD , so 1st device will turn off , then second one will try to give full load current it will hit ILIM & TSD , that way start up might not happen. If you want to turn on both the devices at the same time then you can short PG of both the devices together and use the PG to enable downstream. Best Regards, Mani.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1653887/tps25983-tps25983-current-limit-accuracy/6381777Sat, 13 Jun 2026 16:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5f71ed14-25c8-47e4-a9f0-cffeb8cee6f5Mani RayHello Hank, Thanks for reaching out. Can you please let me know that where are you measuring the current? You are not including any other load or supply current during measurement. Best Regards, Mani.https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1655118/max3223-transmitter-section-failure-of-max3223ipwSat, 13 Jun 2026 14:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5180ae03-b681-44ea-8596-92e8d0cd77ceAnurag BajpaiPart Number: MAX3223 Hi in one application for MAX3223IPW , the force on is connected with invalid bar pin with zero ohm resistor. By mistake the force on is also connected with ground using zero ohm resistor. Initially the ic was working fine, now the tranmit section on RS 232 is sending garbage while the recive section of rs232 of ic is working fine. Can you tell due the invalid bar pin is connected to ground has done the damage to the IC? Thank you.Industrial AutomationMAX3223https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1653497/tps24750-suitability-for-12v-startup-with-10-000uf-load-capacitance-and-active-load-current-at-low-vout/6381770Sat, 13 Jun 2026 14:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:739ceae4-7927-4ce6-99f9-2dbe8f9ae427Mani RayHello Conor, TPS25990 is the best device for this application. Please let me know if you need any support for TPS25990. Best Regards, Mani.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1653189/tps25983-startup-tsd-auto-retry-behavior-and-alternative-device-recommendation/6381769Sat, 13 Jun 2026 14:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5ed0f243-1228-4e7e-8023-b0cb62a79dc6Mani RayHello Conor, TPS25990 is the best device for this application. Please let me know if you need any support for TPS25990. Best Regards, Mani.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1645087/bq41z50-bq41z50evm-unable-to-charge-or-discharge/6381767Sat, 13 Jun 2026 14:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6b9833e6-719f-45d6-b340-89f2be92bb0eSteve HawnHi Anthony, Here's a log file for review. e2e.ti.com/.../0844.BQ-Log.log Thanks, -Stevehttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1655069/tms320f28p551sg-how-to-display-clb-diagram-with-ccs-v20-4/6381765Sat, 13 Jun 2026 14:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2d19ed51-3f8a-4f3c-add3-ee586fd97888Venkata Praneeth SominaIf you have further queries please post them here. Closing this thread now.https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1655117/tms320f28p650dk-random-issues-debugging-flashingSat, 13 Jun 2026 13:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:45481ef3-293f-4833-8fe2-3cd979dd0f9aAyden BourdeauPart Number: TMS320F28P650DK Other Parts Discussed in Thread: UNIFLASH Hello, Up until fairly recently I have had no problems on a custom board with the P65x. A few weeks ago I began development on a SSBL and noticed that a bunch or issues arrose with debugging and flashing the controller after 4-6 months of no problems. lash banks that the user would like the flash plugin to erase (in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI) C28xx_CPU1: Warning: Failed unlocking device (zone 1) after reset. C28xx_CPU1: Warning: Failed unlocking device (zone 2) after reset. C28xx_CPU1: Trouble Setting Breakpoint with the Action "Remain Halted" at 0x10058: (Error -1066 @ 0x10058) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 20.0.0.3283) C28xx_CPU1: Breakpoint Manager: Retrying with a AET breakpoint C28xx_CPU1: GSxMSEL register configured correctly C28xx_CPU1: BankMuxSel register configured correctly C28xx_CPU1: Trouble Setting Breakpoint with the Action "Remain Halted" at 0x1010c: (Error -1066 @ 0x1010C) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 20.0.0.3283) C28xx_CPU1: Breakpoint Manager: Retrying with a AET breakpoint C28xx_CPU1: Error executing PLL configuration algorithm. Operation cancelled. (0x0) C28xx_CPU1: Perform a debugger reset and execute the Boot-ROM code (click on the RESUME button in CCS debug window) before erasing/loading the Flash. If that does not help to perform a successful Flash erase/load, check the Reset cause (RESC) register, NMI shadow flag (NMISHDFLG) register and the Boot-ROM status register for further debug. C28xx_CPU1: File Loader: Memory write failed: Unknown error C28xx_CPU1: Breakpoint Manager: Retrying with a AET breakpoint After doing some research, it looks like the device cannot unlock specific zones in flash to program but I have never worked with the DCSM? It seems the only way to fix this is to perform a bunch of memory operations via Uniflash (don't know why this works is it a different GEL file maybe?) like erasing all of flash and reflashing several times and if I am lucky it will recover. I also noticed that most of the scripts on Uniflash require me to manually reset the controller with our push button or else they hang on OnTargetConnect(). I tried to revert all my changes from _cint00 and the linker cmd file back to what they were and now none of my projects can load or flash. Any suggestions on how to proceed with debugging if / how the device was locked would be great. I followed the instructions in a similar forum with no success. https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1066378/tms320f280049-trouble-setting-breakpoint-with-the-action-remain-halted-at-0xc0d4UniFlashTMS320F28P650DKhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1655116/tps23730evm-093-request-for-tps23730evm-093-altium-pcb-design-files-for-layout-and-routing-referenceSat, 13 Jun 2026 13:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:71979e40-45f7-4a42-adc6-364a4925cc09Alinda ArnoldPart Number: TPS23730EVM-093 Other Parts Discussed in Thread: TPS23730 Hello TI Team, I am developing a custom IEEE 802.3bt PoE-powered IP camera and I am using the TPS23730EVM-093 as my primary reference design. I have already reviewed the TPS23730 datasheet and the TPS23730EVM-093 User Guide, including the schematics, BOM, and PCB layout images. However, I would like to study the actual PCB implementation in greater detail, particularly the routing and placement techniques used in the reference design. Could you please let me know whether the TPS23730EVM-093 Altium source files are available, including: Altium PCB project files (.PrjPcb) PCB layout files (.PcbDoc) Schematic files (.SchDoc) My primary interest is understanding: PoE front-end layout and routing RJ45 and Ethernet transformer placement Bridge rectifier placement TPS23730 placement strategy Isolation boundary implementation Grounding strategy (VSS, RTN, PGND, GND) High-current power routing EMI/ESD layout considerations Transformer and MOSFET placement Return-current paths and power-loop optimization The layout figures provided in the user guide are helpful, but having access to the editable design files would greatly assist me in understanding the routing methodology and applying TI's recommended layout practices to my own design. If the Altium files are not publicly available, I would appreciate any additional PCB layout resources, design databases, or application notes that can help guide the implementation. Thank you for your support. Best regards, Alinda ATPS23730Portable ElectronicsTPS23730EVM-093https://e2e.ti.com/support/isolation-group/isolation/f/isolation-forum/1654574/isow1050-no-stock-to-order/6381763Sat, 13 Jun 2026 13:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:391fb308-b30a-47f0-bba9-74b40c7abbf5Joe SivaswamyHi Varun, what is the link on Linkedin to connect with youhttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1654077/lp-am261-biss-c-not-work-properly/6381761Sat, 13 Jun 2026 13:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:68d9bde3-f3ed-4149-b5fc-c8d74c158ee0Dhaval KhandlaHi Can you please try with MOTOR-CONTROL-SDK-AM261X SDK 2025.00.00.06 release from ti.com? Regards Dhavalhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1647676/tps2330-schematic-check/6381758Sat, 13 Jun 2026 12:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3b42d3c5-e84e-484c-8e11-b746b1127171Mani RayHello Jeff, I believe that IC damaged because of EOS. Please go through below application note for details. https://www.ti.com/lit/an/slyt862/slyt862.pdf?ts=1770828756509&ref_url=https%253A%252F%252Fe2e.ti.com%252F Best Regards, Mani,https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1655115/ds90ub983-q1-compatibility-inquiry-ds90ub983-q1-with-ds90ub948-q1-for-dp-to-dual-lvds-display-applicationSat, 13 Jun 2026 12:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:af69c1bc-7ed1-4737-b5c7-9590094c3510Madhan KumarPart Number: DS90UB983-Q1 Other Parts Discussed in Thread: DS90UB948-Q1 I am evaluating a display architecture and would like to confirm the compatibility of the selected devices. System Architecture: Board 1: Mini Display Port (mDP) input from host system DS90UB983-Q1 serializer Coaxial cable output Board 2: Coaxial cable input DS90UB948-Q1 deserializer Dual LVDS output to display panel(s) The intended signal path is: mDP Source → DS90UB983-Q1 → Coaxial Cable → DS90UB948-Q1 → Dual LVDS Display I would like to know: Is DS90UB983-Q1 compatible with DS90UB948-Q1 in this configuration? Can the DS90UB983-Q1 establish a valid link with the DS90UB948-Q1 over a coaxial cable? If they are not directly compatible, could you please recommend the appropriate serializer/deserializer pair for converting a Mini Display Port source to Dual LVDS displays over a coaxial cable? Are there any reference designs, application notes, or design considerations relevant to this implementation? Display requirements: Interface: Mini Display Port input Transmission medium: Coaxial cable Display interface: Dual LVDS Resolution: 1920 * 1080 Refresh rate: 60Hz Thank you for your support. I look forward to your guidance.DS90UB983-Q1DS90UB948-Q1