https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1697587/am3359-prp-solution/6539097Sun, 15 Nov 2026 10:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0b646c30-37e9-4e1a-8796-68185bb4e922PratheeshGangadharAM335x support is predominantly maintained on Linux OS, we are in the process of upstreaming PRP and HSR support. If you are looking for RTOS support then you can look at IND-COMMS-SDK Software development kit (SDK) | TI.com for software and AM2612 data sheet, product information and support | TI.com for 100M HSR/PRP AM2434 data sheet, product information and support | TI.com for gigabit HSR/PRP .https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1697654/am6442-enet-cpsw-icssg-at-the-same-time/6539096Sun, 15 Nov 2026 10:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2cc9ba04-0de9-4970-bfa2-0e2f3aced7a3PratheeshGangadharShort answer Yes — CPSW and ICSSG can run simultaneously with the Enet driver. The AM64x/AM243x family supports up to five concurrent external Ethernet ports, with pinmux overlap on only one CPSW3G0/PRU1_ICSSG instance combination 1 . Your target split (1× CPSW + 2× ICSSG) is well within that limit. CPSW and ICSSG use separate, distinct Ethernet drivers, which is also what gives you true port/interrupt isolation between the two domains — something not achievable between two ports of the same CPSW instance 2 . Typical partitioning: ICSSG on one R5F core, CPSW on another, communicating via IPC/shared memory with Enet-LLD on each 3 . Example applications Reference What it shows system_cpsw_icssg test (under enet_icssg_tcpserver ) Buildable example loading separate .out files for the ICSSG and CPSW cores — four IPs via ICSSG, one via CPSW, all ports in MAC mode 3 enet_multicore_lwip (mcupsdk-core GitHub) The reference TI points to for the combined CPSW+ICSSG multicore case 4 SPRADH8 system example 4 ICSSG MAC ports + 1 CPSW MAC port on AM64x, Enet-LLD, R5F_0/R5F_1 split 5 Note: ICSSG port count is freely scalable — the four ICSSG0/ICSSG1 ports can be configured as two 2-port switch pairs, four MAC ports, or any mix, so scaling to just two ICSSG ports alongside a CPSW MAC port is a documented configuration 6 . Gap to flag: There is no pre-built SDK example titled or described as exactly "1 CPSW MAC-to-MAC port + 2 ICSSG EtherNet/IP ports" 7 , and official documentation for this combined use case was still in progress as of the referenced TI thread 4 . Expect to adapt enet_multicore_lwip . TMDS64EVM: all three RJ45 concurrently Yes, with one board-specific caveat. The EVM has three RJ45 ports: J14 (DP83867) → CPSW_RGMII1 — dedicated CPSW 8 J21A (DP83869) → PRG1_RGMII1 , dedicated to the ICSSG domain 9 J21B (DP83869) → signals multiplexed between CPSW_RGMII2 and PRG1_RGMII2 , with a GPIO-controlled mux selecting CPSW vs. ICSSG for that connector's MDIO/MDC lines 8 So the muxed port must be assigned to ICSSG, and the second CPSW port plus its MDIO mux must be disabled, giving exactly 1× CPSW + 2× ICSSG 10 . Under Linux the default assigns the muxed port to CPSW; apply k3-am642-evm-icssg1-dualemac.dtbo in U-Boot to hand it to ICSSG in Dual-EMAC mode ( k3-am642-evm-icssg1-dualemac-mii.dtbo for MII) 11 . This is confirmed working on an AM64x EVM: ICSSG on CoreR0-0 (2 ports) + CPSW on CoreR0-1 (1 port) 4 . AM64x/AM243x Hardware Design Guide (SPRAD67D) AM64x EtherCAT Application Note (SPRADH0) Multi-Port Ethernet App Note (SPRADH8), p.22 E2E: AM6442 Enabling 3 Ethernet Ports SPRADH8, p.13 — ICSSG and CPSW allocation SPRADH8, p.12 AM64x MCU+ SDK Examples Index TMDS64EVM User's Guide (SPRUJ63D), p.36 SPRUJ63D, p.37 E2E FAQ: AM6442 R5F PRU Ethernet alongside Linux A53 Processor SDK Linux: PRU_ICSSG Ethernet Enet Layer 2 ICSSG Example MCU+ SDK Release Notes 8.4.0 AM64x/AM243x Design Recommendations (SPRACU5E), p.84 MCU+ SDK Release Notes 8.6.0 E2E: AM6442 ICSSG Dual MAC issues SPRADH8, p.1https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1697711/msp-exp430fr5739-requesting-a-replacement-chip-for-msp430fr5739srhat/6539093Sun, 15 Nov 2026 09:48:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:939b18ab-324d-46e7-8947-f986793d3f75fudong chenThis?https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1697711/msp-exp430fr5739-requesting-a-replacement-chip-for-msp430fr5739srhat/6539092Sun, 15 Nov 2026 09:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:10db874a-0a5f-4934-b1af-e48410d4fd8efudong chenM430FR5739SRHATEP?https://e2e.ti.com/support/sensors-group/sensors/f/sensors-forum/1697740/tmp1075evm-need-the-tmp1075evm-specSun, 15 Nov 2026 08:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:636d99d9-4d11-4499-88be-84411ec9880dChen Alex1Part Number: TMP1075EVM hi sir We plan to use the TMP1075EVM in our system. Could you please provide the dimensions, mounting hole information, and mechanical details for this evaluation board? Thank you.TMP1075EVMhttps://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1697739/dlp471tp-dlplcr471tpevm-board-powers-down-pwrgood-drops-d8-on-only-when-j10-dmd-flex-is-connected-no-light-d1-never-onSun, 15 Nov 2026 08:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4f34d259-a4ec-4477-97a7-333986c195b5Tanvi BhanushaliPart Number: DLP471TP Other Parts Discussed in Thread: DLPA3005 Hi, Our DLP LightCrafter Display 471TP EVM produces no light and shuts itself down a second or two after power-on. The fault only happens when the J10 (HSSI1) DMD flex is connected. We'd appreciate any guidance on isolating it. SETUP - EVM software/firmware: 4.5.0 (bootloader and application both updated with the DLP EVM GUI) - 19 V supply, verified with a multimeter EXPECTED (Table 5-1, DLPU105A) D1 (LOCKN) on, D4 heartbeat blinking, D5 (PWRGOOD) and D7 (PROJ_ON) on, light output. OBSERVED D1 never turns on and there is no light output. Before the FW update (either pattern, unpredictable): - D4 blinks ~4 times, then D4 and D5 turn off. D7 stays on and D8 turns on red. - Same as above, but D8 flashes red briefly and then turns off. After the FW 4.5.0 update: - Case 1: D4, D5 and D7 come on normally, D4 never blinks, then D4 turns off, then D5 turns off. D7 stays on and D8 turns on. - Case 2: D4, D5 and D7 come on, D4 blinks once, then D5 turns off. D4 and D7 stay on solid and D8 stays off. GUI - J10 unplugged: "Ready; Curtain", controller responds to commands, DMD field = 0, DMD Error and Communication Error flagged, Event Viewer empty. - J10 connected: the controller answers its first commands, then the connection drops within 1-2 s. Event Viewer stays empty. ALREADY CHECKED - All fans run - Swapping the flex cables made no difference - No visible damage on any board OUR THINKING The controller and PMIC seem fine, since the board runs with J10 unplugged. D5 dropping while D8 comes on looks like the DLPA3005 shutting down on a fault. We suspect a DMD-side fault on the 1.8 V VDD/VDDA rail, or on VOFFSET/VBIAS/VRESET, that only trips once DMD bring-up starts. We also realize that with J10 unplugged, the controller probably never powers up the DMD's high-voltage rails, so we haven't ruled those out. It could also be a communications error between the main board and DMD. QUESTIONS 1. Have you seen this LED/shutdown pattern before, and does it point to a failed DMD or DMD interface board? 2. Which J7/J10 pins carry 1.8 V, VOFFSET, VBIAS and VRESET, and are there expected unpowered resistance-to-ground values we can check against? 5. If the DMD is faulty, what are the repair or replacement options? Thanks!DLPA3005Connected peripherals & printersdlp471tphttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1697737/drv8350-fault-protection-delay-timeSun, 15 Nov 2026 05:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:61bae3a4-9fa7-4b5b-b122-a2cce422f196Colin ChenPart Number: DRV8350 Dear Experts, I would like to know how much time passes, from the moment a fault is triggered in the DRV8350 after the SPI configuration for fault protection is in place, until the PWM signal is disabled. I couldn't find a description of this time in the datasheet. Thank you.DRV8350Roboticshttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1697736/lmg2100r026-continuous-output-currentSun, 15 Nov 2026 05:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:78c2f5b5-7f56-4e4a-abfc-2f995e610be8Colin ChenPart Number: LMG2100R026 Dear Experts, I noted from the LMG2100R026 datasheet that this chip is described as a 100V 53A GaN device. I would like to know under what voltage and temperature conditions this 53A rating was measured. What is the RMS current of the chip? Regarding the LMG2100R026, how can I roughly estimate the continuous output current of the chip at a given temperature? For example, at a case temperature of 100°C, what continuous output current does the chip support? I look forward to your reply. Thank you.LMG2100R026Roboticshttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1697502/am2634-q1-can-tx-failure-on-frame-a-in-mcal/6539089Sun, 15 Nov 2026 04:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6ac1f4f9-bacb-4640-9372-e273f726a8d0Jenney NiHi Pranav, What issues can this trigger? Could it cause blocking? Regards, Jenneyhttps://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/1697322/opa593-when-the-en-pin-is-turned-off-a-high-voltage-pulse-is-present-at-the-output/6539088Sun, 15 Nov 2026 04:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:01e027bd-f25e-457a-aa7f-e8e6a0782943stephen liyes, this is schematic: , may help you.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1697575/bq76200-bq76200-charge-pump-issue-when-cp_en-is-active-after-boot/6539087Sun, 15 Nov 2026 03:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:acc243a8-cba3-4bea-80ad-e70a3d9fd5a0Vinay MurthyVia a controller we have controlled the inputs lines of the BQ76200 IC. Flashing SW we are doing on the dedicated controller not on this BQ76200.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1691512/tps4800-q1-1v-voltage-seen-when-gate-driver-of-tps48000-is-off/6539086Sun, 15 Nov 2026 03:14:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f8c8d0c2-d678-4bb2-8c29-ef82e197c06bNick LuHi, Sarah Please refer to this file for clarification. Thanks! e2e.ti.com/.../Summary-of-scopes.pptxhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1697734/ucc24630-ucc24630--24vSun, 15 Nov 2026 01:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:74e65fb8-91c1-4a0f-a256-0939618f296bjohn PucciPart Number: UCC24630 Other Parts Discussed in Thread: LM5023 , , 24V 2.5A.pdf Hello TI Team, We are trying to implement UCC24630 synchronous rectification in the 24 V, 2.5 A LM5023 flyback power supply shown in the attached WEBENCH PDF. The input range is 85–265 VAC. The attached report shows the original diode-rectified design. We selected the VPC and VSC divider resistors using the equations in the UCC24630 datasheet. All our divider resistors have 1% tolerance. The results are: In our 12 V power supply, the UCC24630 operates correctly using the same calculation method. In the 24 V power supply, it operates at low load, but the UCC24630 becomes damaged when the load is increased. The SR MOSFET tested functional after the controller failure. The 24 V power supply operates correctly with replacement of UCC24630 with no load. We also checked the resistor calculations against TI’s document “Using the UCC24630EVM-636.” Its published component values are: RVPC1 (R15) = 576 kohm RVPC2 (R16) = 10 kohm RVSC1 (R17) = 590 kohm RVSC2 (R18) = 47 kohm Using the nominal current-emulator gain ratio of 4.15, these values imply: Margin factor = (576/10 + 1) / [4.15 x (590/47 + 1)] Margin factor = 1.04186 Therefore, the selected EVM resistors correspond to approximately 4.19% nominal margin in the RVSC calculation, rather than the initial 10% margin represented by 1.1. The datasheet’s Section 8.2.3.2 also shows a calculated R17 of 554 kohm using the 1.1 factor, then uses 590 kohm for the subsequent calculations. Could you please clarify: Why was 590 kohm selected for the EVM, and how should we determine the appropriate RVSC timing margin for our 24 V design? Are there additional requirements for 24 V operation that could explain the controller damage despite successful operation in our 12 V design? Which measurements at VDD, VPC, VSC, and DRV would help identify the failure mechanism? Thank you for your assistance.Industrial AutomationUCC24630EVM-636UCC24630LM5023https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1696446/am6422-dmsc-security-handover-on-am64x/6539083Sat, 14 Nov 2026 22:44:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3fb39ed9-fc2e-434d-a68c-8dce4851781bDmitri VerechtchiagineHi Prashant, Thank you for the explanation. Now I have another problem. I am trying to setup a firewall for a region in DDR using firewall 1 and when enabled the firewall ignores the specified address range and blocks the whole DDR instead. I tried this on R5F and A53 and using TISCI and by directly writing to the firewall configuration registers after security handover. I tried using region 0 and region 1 registers and it didn't make a difference. Thank you, Dmitrihttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1697733/tms320f28379d-request-for-ready-to-flash-foc-software-3-phase-and-6-phase-pmsm-sic-inverter-evaluationSat, 14 Nov 2026 21:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9f5cbe69-63c5-46d4-bb82-42c64b1d876fsaikumar kayyam,Part Number: TMS320F28379D Hello Texas Instruments Team, We are currently evaluating motor control solutions for our power electronics projects We are interested in using the Wolfspeed 300 kW SiC inverter reference design from wolfseed and ti02014 traction inverter as the foundation for our inverter development. We would like to know whether TI can provide complete, ready-to-flash Field-Oriented Control (FOC) software for both three-phase and six-phase PMSM motors. Our primary requirement is to have a working software platform where we can modify motor and inverter parameters according to our application without developing the complete FOC algorithm from scratch. Specifically, we would like to have the flexibility to configure: Motor parameters, including Rs, Ld, Lq, pole pairs, flux linkage, speed, and current limits. DC-link voltage, SiC MOSFET ratings, switching frequency, dead time, and protection limits. Three-phase and six-phase motor control configurations. Dual three-phase inverter operation with a single resolver for rotor position feedback. Current control, speed control, torque control, and PWM generation. Current and voltage sensor scaling and fault protection. We are considering TI C2000 controllers, including the TMS320F28379D, for our development. Could you please confirm whether TI has an existing FOC software package, reference project, or evaluation firmware that we can directly flash onto the controller and customize for our inverter hardware? We would also appreciate information regarding software licensing, source-code availability, required development tools, and any technical support available for integrating the software with the Wolfspeed 300 kW reference inverter. Our goal is to accelerate inverter evaluation and testing while maintaining the flexibility to modify the motor parameters, SiC power modules, and inverter operating conditions. We look forward to your recommendations. Best regards, SaiSoftware-defined vehicleTMS320F28379Dhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1677428/lmk05318b-unexpected-1pps-phase-offset-between-priref-and-out7/6539082Sat, 14 Nov 2026 21:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:87b9112e-8c05-4d84-b10b-125ecebf9461Octo HalsemaHi Serizawa, I was not able to reproduce the issue under normal conditions. Only when the OCXO is heating up and not yet stable the phase offset was sometimes seen on an older board revision. The software driver soft-resets the LMK after OCXO ready to overcome that scenario. The GNSS receivers power supply has been reviewed and decoupling measures has been taken to give the LMK05318B a more clean PLL supply. It could have been an indirect effect of power supply ripple of the GNSS receiver on the OCXO, effectively affecting (modulating) the XO frequency. The 1.0A buck/boost converter was replaced by 1.8A TPS63000 to give the GNSS receiver and LMK sufficient clean power during startup. Unfortunately, I do not have access to the EVM to be able to make a comparison.https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1697732/adc12qj1600evm-adc12qj1600-evm-gui-write_register-issue-win-11Sat, 14 Nov 2026 21:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2f37d836-be26-421d-9153-a44a5c3c275bMarco CassinerioPart Number: ADC12QJ1600EVM Other Parts Discussed in Thread: ADC12QJ1600 Hello, I am trying to use the ADC12QJ1600 EVM GUI to configure the respective evaluation board. Software installed without issues but I get this error when I try to program Clocks and ADC: "Error 1379 occurred at ADC12QJ1600 EVM GUI.py, line 57 in write_register LabVIEW_Exception: Open Application Reference in ADC12QJ1600 EMV GUI.lvlib: GetApplication.vi->ADC12QJ1600 EVM GUI.lvlib:Write Register.vi I tried updating the NI RTE but that didn't solve the problem. Has anyone been able to use the GUI? If so, how? Thanks, MarcoADC12QJ1600ADC12QJ1600EVMhttps://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/1697731/cc1312psip-cc1312psip-current-consumption-of-compb-reference-dac-in-standbySat, 14 Nov 2026 20:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:38d11af5-ebec-4e53-be02-988b2a9d7b41Yaşar BOLATeXPart Number: CC1312PSIP Other Parts Discussed in Thread: CC2650 Hello, We plan to use the low-power clocked comparator (COMPB) on CC1312PSIP to wake up the Sensor Controller, and then the System CPU, from standby. The Sensor Controller is idle and only COMPB with the Reference DAC as its reference is enabled. The CC1312PSIP data sheet (SWRS293) gives 0.9–1.0 µA for standby, but section 8.15.4.1 has no current consumption value for the clocked comparator. The CC2650 data sheet listed 362 nA for it. Could you please tell us: 1. What is the typical additional standby current with COMPB enabled? 2. What is the additional current of the Reference DAC and the LPM bias module when they provide the COMPB reference in standby? 3. Is there an example project (Sensor Controller Studio or SDK) that uses the COMPB event trigger to wake up from standby? Conditions: VDDS = 3.0–3.6 V, 25 °C, DC/DC enabled, SCLK_LF from XOSC_LF. Thank you. YaşarCC1312PSIPCC2650https://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/1697424/pga309evm-usb-daq-board/6539080Sat, 14 Nov 2026 19:10:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ea0a1047-0938-4408-bf4a-33e4c02b0e9fRobbHi Ashley, Is this test board (refer attached image) similar to the PGA309EVM USB. I think the difference is in the interface, USB and RS232 and the feature to provide VIN. Thanks to Carolina for providing this photo. I wonder where I can buy this board.https://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/1697424/pga309evm-usb-daq-board/6539079Sat, 14 Nov 2026 19:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:be9d9825-61fd-4e5f-bd53-5e77404a46ffRobbThanks Carolina this helps me figure out the connections. This project was handed over to me by the engineer working on it who wasn't halfway figuring things out. I will try reconnecting the MULTICAL based on the schematic in the file.