Other Parts Discussed in Thread: ADC08D1020 Hi,all
I have confused about power up sequence about ADC08D1020.
The datasheet said "Be sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than …
Other Parts Discussed in Thread: ADC08D1020 , LMH6552 , LMX2541 , LM95221 , TMP451 , LP3878 , LM95235 HI, all
Can the ADC08d1020 IO used to configure ADC be directly connect to 1.9V whitch is the supply of this ADC?
why in the evaluated board the I/O is connected…
Hi，Jim
I have new questions and hope can get your help.
It's about the ADC08D1020 IO supply.In the reference design of TI ,the control IO are drive by 1.8(pull up by 1.8v and connected to the 1.8v bank of FPGA), but now can i drive these pins use…
hi,
Does OR/DLCK2 and DCLK have the same performance when OR/DLCK2 is used as DCLK2 to receive high rate data?
I am looking forward advice of using dclk2 .
Thanks .
Other Parts Discussed in Thread: ADC08D1020 , ADC08D1520 Hello,
I am looking for a more detailed explanation of what occurs during the calibration process of the ADC08d1020 .
Looking at the datasheet it looks like the analog input differential termination…
Other Parts Discussed in Thread: ADC08D1020 Hello,
Could you please kindly let me know below questions of ADC08D1020 and LM97600?
1) If stop the clock input to ADC , and restart the clock input after 1 second ,
Can both ADCs output best performance data…
Other Parts Discussed in Thread: ADC08D1020 Hello,
I'm developing a data acquisition system for a swept source optical coherence tomography system. I would prefer to directly sample of the k-clock to avoid the processing step of re-sampling the data…
Hi Bugra
The ADC08D500 device does not include an output data test pattern. There is a pin compatible device which does have that feature, the ADC08D1020.
It is possible to design a board that can accommodate both devices, please see this document for…
For 6 inputs at 1GSPS, the ADC08D1020 is the best solution.
With the ADC08D1020 (quantity of three devices), in 1:1 (non-demux), the output data will be at 1 Gbit/sec on six 8-bit LVDS buses. The DCLK will be operating at 500 MHz (DDC clocking).
If that…
