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  • ADC08DJ3200: ADC input tracing

    Resolved
    Part Number: ADC08DJ3200 Dear TI, I am tracing a board with ADC08DJ3200. It seems to me that in the ADC's EVM, the differential inputs of channel A and B are traced as 50 Ohm single ended traces (first image). In my layout, is it better to trace these…
    • Resolved

  • ADC08DJ3200: JESD204C IP - RX clock and sysref issues

    TI Thinks Resolved
    Part Number: ADC08DJ3200 Hi everyone! We have a project where we want to connect an ADC08DJ3200 to an Kintex ultrascale (KCU105 from Xilinx). I've started to use the JESD204C IP from TI in simulation and with a loopback board to learn how it works before…

  • ADC08DJ3200: Noisy spikes appear in the signal

    TI Thinks Resolved
    Part Number: ADC08DJ3200 Other Parts Discussed in Thread: TSW14J57EVM Hi TI, I use ADC08DJ3200EVM (together with TSW14J57EVM to capture data). I use single channel (A) differential signal coupled through 100nF DC blocking capacitors. Everything works…

  • ADC08DJ3200: Verilog HDL example code of ADC08DJ3200 JESD204

    TI Thinks Resolved
    Part Number: ADC08DJ3200 Do we have an example code of JESD204 in Verilog DHL
    • Answered

  • ADC08DJ3200: ADC08DJ3200 Vs ADC12DJ3200 operating on Jmode 5

    Resolved
    Part Number: ADC08DJ3200 Other Parts Discussed in Thread: ADC12DJ3200 , Hi, Our requirement is operating ADCXXDJ3200 on 8 bit mode for 5 GSPS. We have already tested the operation using ADC12DJ3200 Operating on Jmode 5. Since we do not require any…
    • Resolved
    • Answered

  • RE: ADC08DJ3200: Possible to run the ADC08DJ3200 @ full rate (3.2 GSPS x 2 channels) with TSW14J56revD EVM board?

    Resolved
    Hi Steve The firmware team reports that the actual saved data in the .bin file is OK for Ch1 and Ch2 on TSW14J56. So you can get up to 1073741824 samples per channel in JMODE7 (8b dual channel). Unfortunately there aren't any improved capture depth…
    • Answered

  • ADC08DJ3200: Trying getting erroneous test pattern out of jesd204b

    Resolved
    Part Number: ADC08DJ3200 Running the chip at 6.4GHz, 16 Channels of data over JESD204 is working correctly and subclass 0 is running smoothly to a Xilinx MPSoC. When I run test patterns from the ADC I get bad data on some channels. Always the same bad…
    • Resolved

  • ADC08DJ3200: work with Xilinx 7A100T GPT 6.6Gb/s 8Lanes

    TI Thinks Resolved
    Part Number: ADC08DJ3200 Hello Team, Customer is asking if ADC08DJ3200 with input clock 2.5GHz and operates as single channel so will be 5GHz. Can customer use Xilinx 7A100T GPT 6.6Gb/s 8Lanes to communicate with it? Thanks! Andrew

  • Compiler: TSW14J57EVM+ADC12DJ3200/ADC08DJ3200

    TI Thinks Resolved
    Other Parts Discussed in Thread: ADC12DJ3200 , ADC08DJ3200 , TSW14J57EVM Tool/software: TI C/C++ Compiler I want to know if it can write data to hard disk in real time at 6.4 Gsps sampling rate through its USB 3.0 interface. （TSW14J57EVM+ADC12DJ3200/ADC08DJ3200…
    • Answered

  • ADC08DJ3200: Number of JESD204B lanes required for 5 Gsps

    Resolved
    Part Number: ADC08DJ3200 Hello, I'm considering using [ADC 08 DJ 3200] with 5 Gsps (Single-Channel Mode). I want to minimize the GTX of the FPGA to be used, Can it be changed by register setting of the device? Or may it need all of DA 0 - 7 &…
    • Resolved

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