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    Answered

  • ADC09QJ1300: TI204C-IP JESD FPGA IP interface

    Resolved
    Part Number: ADC09QJ1300 Tool/software: Hello, I'm admittedly new to JESD204 interfaces, and trying to get a minimalistic design up and running with a single converter (ADC) while understanding what is required for evolution of the design later. …
    • Resolved

  • RE: ADC09QJ1300: ADC09QJ1300 related issues

    Hello Jeno, Can you please share how you are configuring the ADC, the register writes to the part. Additionally the block diagram you shared initially is different than the one in the datasheet, and it requires specific register writes to the ADC in…

  • ADC09QJ1300-Q1: ADC09QJ1300-Q1 AMI simulation model

    TI Thinks Resolved
    Part Number: ADC09QJ1300-Q1 Other Parts Discussed in Thread: ADC12QJ1600 , , ADC09QJ1300 hi， The AMI simulation model for ADC09QJ1300-Q1 on TI's official website is ADC12QJ1600. Can ADC09QJ1300-Q1 also be used? If not possible, could you please help provide…

  • ADC09QJ1300: how to keep Dither in the output data

    Part Number: ADC09QJ1300 The part has internal dither. controlled by Register 0x9D. my requirement is to turn on the dither and rather than subtracting it out by the device (normal mode of operation) i would like to keep it in the output sample stream…

  • RE: ADC09QJ1300: Unstable link issues

    Amy, Can you share a schematic and layout of the clock connections to the adc please. I think this could be the problem. Best, Eric

  • RE: ADC09QJ1300: output messy code

    Closing due to no response from customer. Thanks, Rob

  • RE: ADC09QJ1300-Q1: TRIGOUT output is unhealthy

    Hello, Sorry for the delayed response. The correct clock frequency for the fpga reference will be dependent on the way you have configured your receiver on your FPGA. Can you let me know what that frequency is. Thanks Eric
    • Answered

  • ADC09QJ1300：How to extract samples from JESD204C IP output data

    Resolved
    Part Number: ADC09QJ1300 Hello, I used Xilinx FPGA and ADC09QJ1300 to complete the design of JESD204C. At present, I can see the IP output data of JESD204C of Xilinx in Vivado. As shown in the figure, I use JMODE 8, and the output port of IP is a 256bit…
    • Resolved

  • ADC09QJ1300: The internal seders PLL of the device is easy to lose lock

    Part Number: ADC09QJ1300 Hi Team, The internal seders PLL of the device is easy to lose lock. Adc09qj1300 adopts jesd204c 66/64b coding. At present, customer project is 4lane interface, 4 channels AD, and the communication rate is 14.85Gbps. Through the…

  • ADC09QJ1300-Q1: ADC TIRGOUT has no output

    TI Thinks Resolved
    Part Number: ADC09QJ1300-Q1 Hi Team, Pin configuration: PD is configured for default pulldown, PLL_EN, PLLREF_SE is pulled high by default, and external clock is selected as 50M signal input. The register configuration address and register values are…

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