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  • ADC09QJ1300: ADC09QJ1300 related issues

    Part Number: ADC09QJ1300 Tool/software: Hi， The project is based on the jesd204b protocol to implement two ad09qj1300 data transmissions, with an external 50MHz crystal oscillator as the clock input, AD sampling rate=1G, JMODE=10, and subclass 1 mode…

  • ADC09QJ1300-Q1: ADC09QJ1300-Q1 AMI simulation model

    TI Thinks Resolved
    Part Number: ADC09QJ1300-Q1 Other Parts Discussed in Thread: ADC12QJ1600 , , ADC09QJ1300 hi， The AMI simulation model for ADC09QJ1300-Q1 on TI's official website is ADC12QJ1600. Can ADC09QJ1300-Q1 also be used? If not possible, could you please help…
    • Answered

  • ADC09QJ1300: Full Scale Range Adjust FS_RANGE does not work

    Resolved
    Part Number: ADC09QJ1300 Tool/software: Hi, cant change the input range using the FS_RANGE register 0x30 regards, joseph
    • Resolved
    • Answered

  • ADC09QJ1300: TI204C-IP JESD FPGA IP interface

    Resolved
    Part Number: ADC09QJ1300 Tool/software: Hello, I'm admittedly new to JESD204 interfaces, and trying to get a minimalistic design up and running with a single converter (ADC) while understanding what is required for evolution of the design later. Part…
    • Resolved

  • ADC09QJ1300-Q1: CRC errors frequently occur on the JESD204C link.

    TI Thinks Resolved
    Part Number: ADC09QJ1300-Q1 Tool/software: Hello, we encountered some issues during the use of the ADC09QJ1300-Q1. Mode Selection: JMODE3/8 - Stability: The JMODE3/8 mode provides stability during signal collection, including empty signal (noise) and…

  • ADC09QJ1300-Q1: JMODE 5 in Table 6-16, max clock rate

    Part Number: ADC09QJ1300-Q1 Tool/software: Table 6-16, 6-17 and 6-18 in the data sheet does not show the max for the input clock range for JMODE 5. The non-Q100 version of the data sheet shows this max at 1040 MHz. I'm supporting an application which…

  • TI-JESD204-IP: Getting to link up / PRBS testing with ADC09QJ1300 via the TI provided JESD IP

    Part Number: TI-JESD204-IP Other Parts Discussed in Thread: ADC09QJ1300 , Tool/software: Hello all, I'm working on my first JESD204 based design which incorporates a TI ADC (ADC09QJ1300) on a custom FMC board and I am trying to make use of the TI-JESD204…

  • ADC09QJ1300: Unstable link issues

    Part Number: ADC09QJ1300 Hi team, Here is a question one of our customers is experiencing, could you please provide some troubleshooting suggestions? I was debugging the ADC09QJ1300 and found that the link was unstable, the AD was configured with…

  • ADC09QJ1300: how to keep Dither in the output data

    Part Number: ADC09QJ1300 The part has internal dither. controlled by Register 0x9D. my requirement is to turn on the dither and rather than subtracting it out by the device (normal mode of operation) i would like to keep it in the output sample stream…

  • ADC09QJ1300: output messy code

    TI Thinks Resolved
    Part Number: ADC09QJ1300 Hello， The clock of ADC09QJ1300 is 100Mhz, and SYSREF=7.8125Mhz, the GLBLCLK and REFCLK of FPGA are 125Mhz, SYSREF is 7.8125Mhz. When used the test mode, he found that JESD204BIP core output messy code. This is configuration…

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