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  • ADC09QJ1300: LVDS connections (SYSREF, TMSTP)

    Resolved
    Part Number: ADC09QJ1300 We are interfacing the device from an FPGA. The LVDS outputs of the FPGA are spec'd at normal LVDS levels, with a minimum output differential of 274mV. The ADC datasheet specifies a minimum differential input voltage is 400mV…
    • Resolved
    • Answered

  • ADC09QJ1300：How to extract samples from JESD204C IP output data

    Resolved
    Part Number: ADC09QJ1300 Hello, I used Xilinx FPGA and ADC09QJ1300 to complete the design of JESD204C. At present, I can see the IP output data of JESD204C of Xilinx in Vivado. As shown in the figure, I use JMODE 8, and the output port of IP is a 256bit…
    • Resolved

  • ADC09QJ1300: The internal seders PLL of the device is easy to lose lock

    Part Number: ADC09QJ1300 Hi Team, The internal seders PLL of the device is easy to lose lock. Adc09qj1300 adopts jesd204c 66/64b coding. At present, customer project is 4lane interface, 4 channels AD, and the communication rate is 14.85Gbps. Through…

  • ADC09QJ1300-Q1: TRIGOUT output is unhealthy

    Part Number: ADC09QJ1300-Q1 Other Parts Discussed in Thread: LMK00304 hi TI engineer： I am having some problems with the ADC adc09QJ1300-Q1.My electrical connection is shown below The corresponding value of the sequential address of my register…
    • Answered

  • ADC09QJ1300: LinkUp flag from the JESD_STATUS register is always low

    Resolved
    Part Number: ADC09QJ1300 Other Parts Discussed in Thread: LMK04828 Hi, I'm working with a board featuring an ADC09QJ1300 set with JMODE7 with 1 GHz sampling clock. I have clock and sysref coming from an LMK04828. After I go through the initialization…
    • Resolved

  • ADC09QJ1300-Q1: ADC TIRGOUT has no output

    TI Thinks Resolved
    Part Number: ADC09QJ1300-Q1 Hi Team, Pin configuration: PD is configured for default pulldown, PLL_EN, PLLREF_SE is pulled high by default, and external clock is selected as 50M signal input. The register configuration address and register values…

  • ADC09QJ1300: interleave channels on ADC09xJ1300 series ADC

    TI Thinks Resolved
    Part Number: ADC09QJ1300 Other Parts Discussed in Thread: ADC09DJ1300 , ADC12DJ2700 Hello guys, I've been reading the datasheet of ADC09xJ1300 series ADCs, I wonder if it's possible to interleave multiple channels on a single chip to achieve a higher…

  • ADC09QJ1300: ADC Design related issues

    TI Thinks Resolved
    Part Number: ADC09QJ1300 Other Parts Discussed in Thread: TSW14J57EVM Hello， Question 1: Are there any FPGA program routines and constraint files for the demo board of ADC09QJ1300EVM？ Question 2: The ADC chips of ADC09xJ800-Q1 and ADC09xJ1300…
    • Answered

  • ADC09QJ1300-Q1: About ADC09QJ1300-Q1 some application question.

    Resolved
    Part Number: ADC09QJ1300-Q1 Hi team, I have some questions about ADC09QJ1300-Q1 as below. thanks 1. Is the sampling rate 1.3GSPS / @9bit per channel? 2. Can I use ADC09QJ1300-Q1 If FPGA Transceiver speed is 12.7Gbps ? 3. PADC09QJ1300AAV will announce…
    • Resolved

  • ADC09QJ1300: skews between input channels

    Other Parts Discussed in Thread: ADC09QJ1300 Hi team I have some questions about ADC09QJ1300 as belows. Are the four sampling channels synchronized? If so, How about the time skew performance between channels？ If the same signal is input to four channels…

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