Part Number: ADC09QJ1300-Q1 Other Parts Discussed in Thread: ADC09QJ1300 Dear teams,
My customer is using ADC09QJ1300. They are not understanding following sentence in the DS 9.2.1.3: A sub-sampling technique is used to interpolate data points to form…
Part Number: ADC09QJ1300-Q1 Hi, TI's experts.
I had some difficulties with my project. I am trying to connect ADC09QJ1300-Q1 to ZYNQ-7000（xc7z100） on my board.
The circuit block diagram is same with 《adc09qj1300-q1.pdf》 Figure 9-1. Typical Configuration…
HI Zeng,
If the FPGA works with normal data and not in test mode to me it looks like a timing issue. Can you add some delay once you enable JESD after setting the test mode and issue if your issue goes away.
Regards,
Neeraj
Part Number: ADC09QJ1300-Q1 Hi Team,
What are the output of 1300?(How many Lanes? and What are the data rate?)
Customer need to know that so as to choose other component.
Part Number: ADC09QJ1300-Q1 Hi team,
I have some questions about ADC09QJ1300-Q1 as below. thanks
1. Is the sampling rate 1.3GSPS / @9bit per channel?
2. Can I use ADC09QJ1300-Q1 If FPGA Transceiver speed is 12.7Gbps ?
3. PADC09QJ1300AAV will announce…
Part Number: ADC09QJ1300-Q1 Hello.
We're going to use two ADC09QJ1300-Q1 in design.
We want to use PLLREFO outputs from the first ADC to send the clock to CLK inputs of second ADC.
The question is about clock stability and jitter.
Will this clocking…
Part Number: ADC09QJ1300-Q1 Hello,
could you please recommend the correct way to align logical levels between ADC09QJ1300-Q1 and an FPGA with 1.8V GPIOs.
In general an FPGA can withstand 1.9V, but the current consumption will be increased.
Can we use 1…
