Part Number: ADC09QJ1300-Q1 Other Parts Discussed in Thread: LMK00304 hi TI engineer：
I am having some problems with the ADC adc09QJ1300-Q1.My electrical connection is shown below
The corresponding value of the sequential address of my register configuration…
Part Number: ADC09QJ1300-Q1
Pin configuration: PD is configured for default pulldown, PLL_EN, PLLREF_SE is pulled high by default, and external clock is selected as 50M signal input. The register configuration address and register values are…
Part Number: ADC09QJ1300-Q1 Other Parts Discussed in Thread: LMK00304 , TPS22917 Hi expert,
I am new to ADC devices, and the customer has several questions about the device application, please kindly find below questions,
1. The output pins of ADC09xJ1300…
Part Number: ADC09QJ1300-Q1 Other Parts Discussed in Thread: ADC09QJ1300 Dear teams,
My customer is using ADC09QJ1300. They are not understanding following sentence in the DS 22.214.171.124: A sub-sampling technique is used to interpolate data points to form…
Part Number: ADC09QJ1300-Q1 Hi, TI's experts.
I had some difficulties with my project. I am trying to connect ADC09QJ1300-Q1 to ZYNQ-7000（xc7z100） on my board.
The circuit block diagram is same with 《adc09qj1300-q1.pdf》 Figure 9-1. Typical Configuration…
Part Number: ADC09QJ1300-Q1 Hi team,
I have some questions about ADC09QJ1300-Q1 as below. thanks
1. Is the sampling rate 1.3GSPS / @9bit per channel?
2. Can I use ADC09QJ1300-Q1 If FPGA Transceiver speed is 12.7Gbps ?
3. PADC09QJ1300AAV will announce…
If the FPGA works with normal data and not in test mode to me it looks like a timing issue. Can you add some delay once you enable JESD after setting the test mode and issue if your issue goes away.
Part Number: ADC09QJ1300-Q1 Hello.
We're going to use two ADC09QJ1300-Q1 in design.
We want to use PLLREFO outputs from the first ADC to send the clock to CLK inputs of second ADC.
The question is about clock stability and jitter.
Will this clocking…
Part Number: ADC09QJ1300-Q1 Hello,
could you please recommend the correct way to align logical levels between ADC09QJ1300-Q1 and an FPGA with 1.8V GPIOs.
In general an FPGA can withstand 1.9V, but the current consumption will be increased.
Can we use 1…