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Showing 9 results View by: Thread Post Sort by
  • ADC09SJ1300-Q1: bypassing the SYSREF window

    mitsuo ono
    mitsuo ono
    Part Number: ADC09SJ1300-Q1 Other Parts Discussed in Thread: ADC09SJ1300 Tool/software: Hello, experts. On our board, the SYSREF window is not very effective and there is a high frequency of Invalid/NotInTable/Disparity errors of TI-JESD204C-IP. I would…
    • 4 months ago
    • Data converters
    • Data converters forum
  • Answered
  • ADC09SJ1300: Questions of JESD204 protocol

    Moon Wang
    Moon Wang
    Resolved
    Part Number: ADC09SJ1300 hi team, My customer asked that which type the differential clock pin(CLK+, CLK-) from ADC09SJ1300 could be connected to, HR bank or HP bank of FPGA? And then, Does the JESD204C of ADC09SJ1300 need to apply the IP which in https…
    • Resolved
    • over 1 year ago
    • Data converters
    • Data converters forum
  • Answered
  • ADC09SJ1300-Q1: IBIS Model

    Ivan Mazur
    Ivan Mazur
    Resolved
    Part Number: ADC09SJ1300-Q1 Other Parts Discussed in Thread: ADC12QJ1600 Hi support team! Im looking for ADC09SJ1300-Q1 IBIS model to do some SI simulations for JESD204B lines. On the device page only the PSpice model is available, but its not acceptable…
    • Resolved
    • over 2 years ago
    • Data converters
    • Data converters forum
  • Answered
  • ADC09SJ1300: about serdes data rate for FPGA selection

    Jerry Chen
    Jerry Chen
    Resolved
    Part Number: ADC09SJ1300 Hi team, My customer would like to evaluate, when ADC09SJ1300 operates in high sampling rate as 1.3Gsps, what the data rate of the serdes will be. They will use four serdes lanes (L=4). This is to select a suitable low cost…
    • Resolved
    • over 3 years ago
    • Data converters
    • Data converters forum
  • Answered
  • ADC09SJ1300: using together with TDA4VM

    Slava Prokopii
    Slava Prokopii
    Resolved
    Part Number: ADC09SJ1300 Other Parts Discussed in Thread: TDA4VM Hello, team. Do I understand correctly, that ADC09SJ1300 con not be connected directly to TDA4VM, and additional FPGA is needed? If so, what the resources do we provide to guide the…
    • Resolved
    • over 3 years ago
    • Data converters
    • Data converters forum
  • Answered
  • TI-JESD204-IP:ADC09SJ1300

    mitsuo ono
    mitsuo ono
    Resolved
    Part Number: TI-JESD204-IP Other Parts Discussed in Thread: ADC09SJ1300 Tool/software: Hello, experts. When I tried the operation of subclass 0 under the following conditions, I encountered a problem where I could not see ADC data. Perhaps TI-JESD204C…
    • Resolved
    • 5 months ago
    • Data converters
    • Data converters forum
  • TI-JESD204-IP:rx_lane_valid signal are transition from ‘1’ to ‘0’

    mitsuo ono
    mitsuo ono
    Part Number: TI-JESD204-IP Other Parts Discussed in Thread: ADC09SJ1300 Tool/software: Hello Experts, We are developing a sampling board. We get rx_lane_valid signal are transition from ‘1’ to ‘0’ once about 15 minutes on our board. At this time,…
    • 10 months ago
    • Data converters
    • Data converters forum
  • Answered
  • ADC09QJ1300EVM:Is it possible to configure the ADC09QJ1300EVM as a Single Channel Device (ADC09SJ 1300)?

    mitsuo ono
    mitsuo ono
    Resolved
    Part Number: ADC09QJ1300EVM Other Parts Discussed in Thread: ADC09SJ1300 ADC09QJ1300EVMをシングルチャネルデバイス(ADC09SJ 1300)として設定することは可能ですか。ADCxxQJxx00 EVM の GUI を使用可能であれば、設定方法を教えていただけますか?
    • Resolved
    • over 1 year ago
    • Data converters
    • Data converters forum
  • RE: ADC09DJ1300-Q1: If we use dual or quad channels, can the rate of each channel reach 1.3G?

    Neeraj Gill
    Neeraj Gill
    Hi Alwen, The ADC09QJ1300 can support full sampling rate of 1.3Gsps in single, dual and quad channel mode. There is also an option to buy the ADC as dual and single channel version along with quad channel option. ADC09SJ1300 data sheet, product…
    • over 2 years ago
    • Data converters
    • Data converters forum

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