Part Number: ADC09SJ1300 hi team,
My customer asked that which type the differential clock pin(CLK+, CLK-) from ADC09SJ1300 could be connected to, HR bank or HP bank of FPGA? And then, Does the JESD204C of ADC09SJ1300 need to apply the IP which in https…
Part Number: ADC09SJ1300-Q1 Other Parts Discussed in Thread: ADC12QJ1600 Hi support team!
Im looking for ADC09SJ1300-Q1 IBIS model to do some SI simulations for JESD204B lines.
On the device page only the PSpice model is available, but its not acceptable…
Part Number: ADC09SJ1300 Hi team,
My customer would like to evaluate, when ADC09SJ1300 operates in high sampling rate as 1.3Gsps, what the data rate of the serdes will be. They will use four serdes lanes (L=4). This is to select a suitable low cost FPGA…
Part Number: ADC09SJ1300 Other Parts Discussed in Thread: TDA4VM Hello, team.
Do I understand correctly, that ADC09SJ1300 con not be connected directly to TDA4VM, and additional FPGA is needed?
If so, what the resources do we provide to guide the customer…
Part Number: TI-JESD204-IP Other Parts Discussed in Thread: ADC09SJ1300 Tool/software: Hello Experts,
We are developing a sampling board. We get rx_lane_valid signal are transition from ‘1’ to ‘0’ once about 15 minutes on our board.…
Part Number: ADC09QJ1300EVM Other Parts Discussed in Thread: ADC09SJ1300 ADC09QJ1300EVMをシングルチャネルデバイス(ADC09SJ 1300)として設定することは可能ですか。ADCxxQJxx00 EVM の GUI を使用可能であれば、設定方法を教えていただけますか?
Hi Alwen,
The ADC09QJ1300 can support full sampling rate of 1.3Gsps in single, dual and quad channel mode.
There is also an option to buy the ADC as dual and single channel version along with quad channel option.
ADC09SJ1300 data sheet, product information…
