Hi Harry,
Please forward to the customer....
Per the attached documents, after setting the base settings there is a tuning step required.
DRC register setting should be adjusted from min to max and DCLK output should be observed on an oscilloscope…
Hi all,
Contents about SNAA073F. AN-2132 The Autosync Feature. Since the circuit diagram of Figure5 and Figure6 does not show the generation principle of FCLK/2, and FCLK/4, Would you teach about detailed operation of the block diagram in 4 binary counter…
Other Parts Discussed in Thread: ADC12D1000 Hi all.
There are the following questions about ADC12D1000.
1. At Time of Combination of One Master-ADC and One Slave-ADC, For example, when one input signal is input into both a master and a slave, Are…
Hi Tony
Sorry the file isn't there. I'll put in a request to get that issue fixed.
The ADC12D1000 IBIS model is equivalent as this entire family of devices have common I/O structures and package. You can find the IBIS model for the ADC12D1000 in that…
Hi,
Do TI have any suggested board design consideration for ADC12D1x00 ADC?
For example, it will be good if TI can let the designers know if trace length match is necessary and the tolerance that is allowable within compromise the performance of the…
Hi Brian,
I have kind of the same problems which you were experiening with the wvdll library. I was following this post, and I have tried too installing the 32 bit version of MATLAB.
When I call the "loadlibrary" command, I still get always the…
