Part Number: ADC12D1620QML-SP Tool/software: To Whom It May Concern,
Hope you're well.
Please allow me to submit following inquiry from the customer and will be grateful if you could kindly provide your knowledge.
<Inquiry from the customer>…
Part Number: ADC12D1620QML-SP To Whom It May Concern,
Hope you're well.
Please allow me to submit the question from customer as attached and we'll be grateful if you could kindly provide your knowledge.
TI_Question about ADC12D1620QML-SP_231002…
Part Number: ADC12D1620QML-SP
Hello,
I have two questions reguarding the sampling clock phase adjust feature on the ADC12d1620QML-SP. In the data sheet it mentions the following...
"The sampling clock (CLK) phase may be delayed internally to the ADC…
Part Number: ADC12D1620QML-SP Hello, Once the AutoSynce is configured correctly by monitoring DCLKs from all ADC via an FPGA or oscilloscope, the same register settings can be used every power cycle? Or every power cycle, users have to again find out…
Part Number: ADC12D1620QML-SP We performed TID radiation testing on an EM part, and found its responsivity dramatically dropped after a small TID dose (well within the specified rating of the FM part).
Is the EM part non-rad tolerant? Or will we see the…
Part Number: ADC12D1620QML-SP Hello,
Looking at the Figure 3 of AN-2132, DCLK could be four different phases in unsyncronized DCLKs and Demux Mode. Does this mean, tOD could actually be the specified value (typ) in the datasheet + either 0 degree, 90…
Part Number: ADC12D1620QML-SP I have a couple questions regarding the lid and it’s risk associated with spacecraft charging.
Does this package have a floating metal lid, or is it grounded or otherwise electrically referenced?
(I've seen…
Part Number: ADC12D1620QML-SP Hello,
I am evaluating two TSW12D1620 eval boards. I am a seeing a fixed -50dBm spur at 400MHz on both cards with or with a the 1.6GHz clock inputted which make me feel it is something I have wrong in my setup. I am following…