Part Number: ADC12DJ3200 Hi Team,
What are the expected voltage levels when the TMSTP_LVPECL_EN is set to '1' ?
Can you tell me how the voltages of LVPECL fit with the requirement for common mode
please refer to section 6.3 - Recommended Operation…
Sorry for late to reply. I miss some mail noticification.
Got it! Thanks!
Can i deliver a clock signal with 3.2GHz to ADC12DJ3200's CLK+/- pins directly? As we know, the ADC12DJ3200 support maximu clk input up to 3200M.
Here are the updated register writes.
SCR_Done does not complete means the sysref is not getting calibrated properly. Can you please make sure the sysref is getting to the ADC?
Part Number: ADC12DJ3200
Our customer used his own ADC12DJ3200 board, 2.4Gbps sampling rate, MODE3，16lane，dual-channel mode, input 264Mhz, -1dBFS single frequency signal, signal source output added low pass filter inhibit harmonics, sample analysis…
Part Number: ADC12DJ3200 Other Parts Discussed in Thread: LMK04828 , , TSW14J57EVM Hi team,
The ADC model is ADC12DJ3200 and the PLL is LMK04828.
The ADC sampling rate is 5 GSPS, the sampling clock provides 2.5 GSPS, and the sysref is 3.90625 MHz, in pulse…
Part Number: ADC12DJ3200 Hi team,
One of our customer's issues, I'm forwarding it below, could you please provide some troubleshooting suggestions
ADC set to JMODE1 mode, lane_rate=6.4G ,K=4 , jesd204B_core lck=160MHz, sysref is both 20MHz, using…
Part Number: ADC12DJ3200 I want to know the digital value of Input Full Scale on the AD12DJ3200(JMODE16) xilinx FPGA Chipscope.
Please check if there is anything missing in ADC setting or getting digital value.
1. Device: AD12DJ3200
- JMODE 16 (Dual…