Part Number: ADC12DJ3200 Tool/software: Hi,
I configured the ADC12DJ3200 to JMODE-6 (8-bit, 4-lanes, dual channel) by setting the following parameters -
Sampling Frequency = 1600 MHz ADC input clock = 1600 MHz line rate …
Part Number: ADC12DJ3200 Tool/software: Hi!
I have a problem when using adc12dj3200. The ADC is set to JMODE 0, but DA1 in the A link is corrupted. I tried using the JEXTRA_A register mentioned on page 119 of the ADC12DJ3200 manual, using DA4 to DA7 instead…
Part Number: ADC12DJ3200 Other Parts Discussed in Thread: TIDA-01022 , LMX2594 Tool/software: In the reference design TIDA-01022, if the SYSREF of the ADC12DJ3200 is implemented as a single pulse clock, does it mean that only DC coupling can be used with…
Part Number: ADC12DJ3200 Tool/software: Dear Technical Support Team,
Could you tell me the example programing of Offset calibration for single-channel mode?
I'd like to compare between my setting and example program.
Best Regards,
ttd
Part Number: ADC12DJ3200 Tool/software: Hi,
My customers are facing a problem when trying to use DJ3200 in a test mode. They tried to enter the test mode with N'=12, and the data they captured for each channel is as below figure1. The Pattern for DA0…
Part Number: ADC12DJ3200 Tool/software: Dear Technical Support Team,
When I checked the operation of this ADC, I input a synthesizer (sine wave), As shown in the attached graph ③, there is a bias of a certain period of about 18 cycles for the resolution…
Hello Mustafa,
A few notes first off these results can be a little misleading because you are not capturing a coherent fft signal, to do this you can do one of two things either adjust the input frequency based on the number of samples you are capturing…
Part Number: ADC12DJ3200 Hi Team,
What are the expected voltage levels when the TMSTP_LVPECL_EN is set to '1' ?
Can you tell me how the voltages of LVPECL fit with the requirement for common mode
please refer to section 6.3 - Recommended Operation…
