Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: ADC12DJ3200 , TSW14J57EVM Hello, I have ADC12DJ3200+TSW14J57EVM evaluation kit, the working mode is JMODE1, it does not work properly with HSDC pro v5.2, but it can collect data normally with…
Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: LMK04828 The ADC12DJ3200EVM manual mentions:
The ADC12DJxx00EVM includes a reference clock input (CLKIN0) which allows the user to sync the LMK04828 to an external 10-MHz reference allowing…
Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: TSW14J57EVM , TSW14J58EVM Hello everyone,
With the TSW14J56 and ADC12DJ3200EVM I want to perform my own FPGA VHDL circuitry with this boards. They actually have their own software (HSDC Pro, that…
Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: ADC12DJ3200
Good afternoon,
We had a design with the Xilinx JESD IP using the ADC12DJ3200 that was working correctly.
We did not test it for a week or so and the next time we turned it on the…
Part Number: ADC12DJ3200EVM Hi,
I tried the dual channel mode of ADC12DJ3200EVM with TSW14J56.
The signal of two channel are 10 MHz +/- clock which displayed in oscilloscope as fig. 1.
fig. 1 10MHz pos/neg clock
Howerver, in the HSDC, the sampled data…
This works for 1 GHz, Thanks Rob. Is there any specific reason for it not working for 800 MHz, and if possible can we make it work for lower frequency clock say 500 or 600 MHz?