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  • ADC12DJ3200EVM: JESD Elastic Buffer Overflow/Underflow

    Resolved
    Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: ADC12DJ3200 Good afternoon, We had a design with the Xilinx JESD IP using the ADC12DJ3200 that was working correctly. We did not test it for a week or so and the next time we turned it on the…
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    • Answered

  • ADC12DJ3200EVM: Working in dual-channel mode, the voltage of one channel's sampled data is reversed

    Resolved
    Part Number: ADC12DJ3200EVM Hi, I tried the dual channel mode of ADC12DJ3200EVM with TSW14J56. The signal of two channel are 10 MHz +/- clock which displayed in oscilloscope as fig. 1. fig. 1 10MHz pos/neg clock Howerver, in the HSDC, the sampled data…
    • Resolved

  • ADC12DJ3200EVM: ADC12DJ3200EVM details to verify compatibility with third party KU115 dev board

    Part Number: ADC12DJ3200EVM The EVM12DJ3200EVM user manual does not specify all board's FMC's IO. Hence I need more information on that, in order to safely verify compatibility with our intended KU115 dev platform. We intend to only use the following…
    • Answered

  • ADC12DJ3200EVM: CDR still locked though the data has bit errors.

    Resolved
    Part Number: ADC12DJ3200EVM Hi team I am sending ADC sampled analog data to my FPGA. I am able to reconstruct the signal at my FPGA. But when i look for the Bit error rate(BER) in the data it is on the high side. Note that my CDR is also locked while…
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    • Answered

  • RE: ADC12DJ3200EVM: External clock mode not working even after hardware modifications specified

    Resolved
    This works for 1 GHz, Thanks Rob. Is there any specific reason for it not working for 800 MHz, and if possible can we make it work for lower frequency clock say 500 or 600 MHz?
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  • RE: ADC12DJ3200EVM: Able to make JMODE2 work but JMODE2 when we change L = 1 and JMODE13 are not working

    Resolved
    Hi Neeraj, Thanks a lot for the detailed explanation, I am now able to proceed with my work. Jaswanth
    • Answered

  • ADC12DJ3200EVM: Number of JESD204 Links

    Resolved
    Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: ADC12DJ3200 In the reference FPGA designs provided by TI for the JESD204B connection to the adc12dj3200, the JESD204 links seem to only have 1 link. The ADC12DJ3200 datasheet mentions 2 links…
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  • ADC12DJ3200EVM: JMODE0, Data Format

    Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: ADC12DJ3200 I am using the example design for the ADC12DJ3200 JMODE0 connected to the KCU105 board. I am having trouble converting the data to a datastream once I get it into chipscope. I ran…
    • Answered

  • ADC12DJ3200EVM: LMX not locking

    Resolved
    Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: ADC12DJ3200 , , LMX2582 Hello, We have an ADC12DJ3200EVM board and have attempted to program the ADC, LMK, and LMX through the ADC12DJ3200 GUI. Currently the LMX and LMK are not locking, are there…
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    • Answered

  • RE: ADC12DJ3200EVM: adc12dj3200evm Not Working - Setup Question

    Resolved
    Hi Neeraj, I thought that I sent this already, my apologies. However, while digging into this board a WHOLE lot, i have other concerns and i think they they would be best answered within a separate thread, so i'm going to consider this one closed.…

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