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  • ADC12DJ3200EVM: What is the step size for ramp test mode ?

    Resolved
    Part Number: ADC12DJ3200EVM Hello Experts, I am using ADC12DJ3200EVM with KCU105. In ramp test mode I am getting the values are 1, 2057, 4113, 6169, and so on. So, could you confirm the test pattern. JMODE = 10 Device clock = 1250 MHz Refclk…
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    • Answered

  • ADC12DJ3200EVM: ADC12DJ3200EVM input signal

    Resolved
    Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: ADC12DJ3200 Hi Team, A Japanese customer bought TI's evaluation board ADC12DJ3200EVM. He has some issues on this EVM board. He can't post by his university email , so I help him confirm these…
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    • Answered

  • ADC12DJ3200EVM: B Link signal inversion for JESD204B outputs on ADC12DJ3200EVM (relative to standard FMC polarity)

    Resolved
    Part Number: ADC12DJ3200EVM We are reviewing the User's Guide for the ADCxxDJxx00 Evaluation Module. In Appendix C, Table C-1, it states that "Red items with _INV in the signal name are inverted with respect to standard FMC polarity.", which refers to…
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  • ADC12DJ3200EVM: ADC jitter characteristics of the ADC12DJ3200EVM

    TI Thinks Resolved
    Part Number: ADC12DJ3200EVM Hi Team, Customer have following concern about the ADC12DJ3200EVM. Please see details below. 1. Trying to compare the characteristics of jitter when undersampling and when oversampling. First, a sine wave is input from…
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  • ADC12DJ3200EVM: CDR still locked though the data has bit errors.

    Resolved
    Part Number: ADC12DJ3200EVM Hi team I am sending ADC sampled analog data to my FPGA. I am able to reconstruct the signal at my FPGA. But when i look for the Bit error rate(BER) in the data it is on the high side. Note that my CDR is also locked while…
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  • ADC12DJ3200EVM: ADC12DJ3200 not interopable with FPGA at high data rate

    TI Thinks Resolved
    Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: ADC12DJ3200 , LMK04828 Hi team I am trying to interop ADC12DJ3200 with FPGA but the link (SYNC status) always stays low. I am supplying clocks to both FPGA and ADC through the clock oscillator…
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  • ADC12DJ3200EVM: Number of JESD204 Links

    Resolved
    Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: ADC12DJ3200 In the reference FPGA designs provided by TI for the JESD204B connection to the adc12dj3200, the JESD204 links seem to only have 1 link. The ADC12DJ3200 datasheet mentions 2 links…
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    • Answered

  • ADC12DJ3200EVM: Working in dual-channel mode, the voltage of one channel's sampled data is reversed

    Resolved
    Part Number: ADC12DJ3200EVM Hi, I tried the dual channel mode of ADC12DJ3200EVM with TSW14J56. The signal of two channel are 10 MHz +/- clock which displayed in oscilloscope as fig. 1. fig. 1 10MHz pos/neg clock Howerver, in the HSDC, the sampled…
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  • ADC12DJ3200EVM: JMODE0, Data Format

    Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: ADC12DJ3200 I am using the example design for the ADC12DJ3200 JMODE0 connected to the KCU105 board. I am having trouble converting the data to a datastream once I get it into chipscope. I ran…
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  • ADC12DJ3200EVM: LMX not locking

    Resolved
    Part Number: ADC12DJ3200EVM Other Parts Discussed in Thread: ADC12DJ3200 , , LMX2582 Hello, We have an ADC12DJ3200EVM board and have attempted to program the ADC, LMK, and LMX through the ADC12DJ3200 GUI. Currently the LMX and LMK are not locking…
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