Hello Ziquan,
" what does this deterministic delay and non-deterministic delay refer to?" This means that some delays will be deterministic (value is know and will stay constant) non deterministic means some delay will change over process, temperature…
Part Number: ADC12DJ5200RF hello,
I have a LVDS output from a Xilinx Ultrascale+FPGA and would like to connect it to the TMSTP inputs.
Unfortunately the DC-coupled TMSTP must meet the low common mode voltage requirements, which is not compatible with…
Part Number: ADC12DJ5200RF Tool/software: Hello, My customer has a question related to the ADC12DJ5200RF datasheet (SLVSEN9F – APRIL 2019 – REVISED JUNE 2024). In Table 6-38 the data transport layer format for JMODE39 in shown using 4 lanes…
Part Number: ADC12DJ5200RF
Is the device clock A)4GHz under the following conditions? Or is it B)2GHz?
For example, I want to transmit 12 bits of data per symbol at 4GSps. The sampling frequency is 4GHz.
A) At this time, 4 tail bits are added to 5 symbols…
Part Number: ADC12DJ5200RF Other Parts Discussed in Thread: DAC39RF10 , Tool/software: Hi,
Customer would like to adopt 5u of ADC12DJ5200RF and 5u of DAC39RF10.
To mount these all components, pattern length is over 100mm.
Could you let me know what is…
Part Number: ADC12DJ5200RF Tool/software: Hello, Related to the following E2E thread, my customer has an additional question. https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1382741/adc12dj5200rf-link-lane-configuration…
Part Number: ADC12DJ5200RF Other Parts Discussed in Thread: TRF1208 Hello,
My customer is considering designing a Zero-IF application using the ADC12DJ5200RF.
Are there any problems implementing Zero-IF applications with ADC12DJ5200RF?
If you have reference…
Part Number: ADC12DJ5200RF HI TI Team,
We are working with ADC12DJ5200RF ADC in our Design. Where we are using a common Analog & Digital GND & we are isolating the Chassis Ground using RC Filter. As per our Requirement we need to have a separate…
Part Number: ADC12DJ5200RF Hi,
We are using x3 ADC12DJ5200 ADC and XCVU11P Devices in my design.
For JESD204 lanes, what is the maximum trace length difference allowed within One channel? Due to placement of ICs and Connections to GTY we are able to a…
