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  • ADC12J1600: Incorrect captured data by JESD204B core

    • Resolved
    Part Number: ADC12J1600 Hi all, I'm trying to develop an algorithm on FPGA to process the sampled

  • ADC12J1600: JESD204B captured data

    TI Thinks Resolved
    Part Number: ADC12J1600 Dear TI experts I'm trying to build the connection between ADC12J1600 and KC705 using the JESD204B protocol. As for now, the data can be sampled by ADC and captured on HSDC Pro software. I'm trying to send the data...

  • ADC12J1600: ADC12J1600: JESD204B data format and data mapping

    TI Thinks Resolved
    Part Number: ADC12J1600 Hi, I'm using ADC12J1600 to sample the data processed by KC705. I have some questions about the output data format of ADC12J1600. Since I'm setting the ADC to "decimation by 4" mode, I've learned about...

  • ADC12J1600: ADC12J1600 to TSW14J10 Timed Out Error on HSDC Pro

    TI Thinks Resolved
    Part Number: ADC12J1600 I am trying to establish connection between ADC12J1600 and a combination of TSW14J10-KC705. Once the connections are established, I am getting the error shown in the picture. Could someone please let me know how this can...

  • RE: IF evaluation kit

    The other consideration is bandwidth requirement. That ultimately determines the sample rate needed. Many of the TI converters support an IF frequency up to and beyond 500 MHz. Estimating the frequency of the input signal sounds like the input signal...

  • ADC12J1600: Fundamental tone attenuation

    • Resolved
    Part Number: ADC12J1600 Hello, I set up ADC12J1600 using HSDC pro as per this thread: https

  • ADC12J1600: Deterministic latency between startups.

    • Resolved
    Part Number: ADC12J1600 I am trying to make the ADC12J1600 work with deterministic latency between

  • RE: ADC12J1600: ADC12J1600 to TSW1400 to HSDC pro

    Hi Mahesh The bandwidths I listed are for the combination of I and Q samples. In Decimate-by-4, DDR, P54 mode the serial bit rate in each lane is 1600 * 2 * 5/4 = 4000 Mbps. Each 16b sample is encoded using 8b10b encoding so there are 20 bits per sample...

  • RE: ADC12J1600: ADC12J1600 to KC705 FPGA: Verilog code

    Hi Jim, Looks like what I need. I will go through the code. Thank you so much.

  • ADC12J1600EVM: ADc12J1600 REV. E3 schematics

    TI Thinks Resolved
    Part Number: ADC12J1600EVM Hello, Could anyone provide a link to the EVM schematic REV. E3 and GUI software for this EVM? Best regards, Dmitri

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