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  stephen malchi

  • 9 months ago
  • Data converters
  • Data converters forum

  ADC12J2700: ZCU102 reference design

  TI Thinks Resolved

  Part Number: ADC12J2700 Hi, I am looking for ZCU102 reference design package to interface with our ADC module from TI. Can you please provide the link. The link provided in this topic is broken https://e2e.ti.com/support/data-converters/f/73/t/816433...
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  jim s

  • over 1 year ago
  • Data converters
  • Data converters forum

  RE: ADC12J2700: reference design for zcu102

  Deepak, We do not have an example with the ADC12J2700 but we have an example that uses another ADC that might be helpful. This can be downloaded from the following link: Regards, Jim
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  Ryan McCourt

  • over 1 year ago
  • Data converters
  • Data converters forum

  ADC12J2700: CAL_STAT bit 2 toggling

  • Resolved

  Part Number: ADC12J2700 We are seeing bit 2 in the CAL_STAT register (0x5b) toggle occasionally
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  Ryan McCourt

  • over 2 years ago
  • Data converters
  • Data converters forum

  ADC12J2700: SYSREF delay calibration

  TI Thinks Resolved

  Part Number: ADC12J2700 We're using an ADC12J2700 with a continuously running SYSREF. To date we've just been using the default RDEL value, but we're seeing some board-to-board (and possible temperature related?) variations where we see the...
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  Errol Leon6

  • over 2 years ago
  • Data converters
  • Data converters forum

  ADC12J2700: Reg 0x006 Datasheet Question

  • Resolved

  Part Number: ADC12J2700 Hello, My customer is using ADC12J2700 . To confirm configuration I/O
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  Layne Jakahi

  • over 1 year ago
  • Data converters
  • Data converters forum

  ADS54J60: sysref input signal with respect to DEVCLK

  TI Thinks Resolved

  Part Number: ADS54J60 Hi, guys, We are migrating from ADC12J2700 toADS54J60. When using ADC12J2700, we can use "RDEL" value to adjust the delay of the SYSREF input signal with respect to DEVCLK. Also, ADC12J2700 provide a "Dirty Capture"...
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  Richard Elmquist

  • over 3 years ago
  • Data converters
  • Data converters forum

  ADC12J2700 JESD204B Questions

  TI Thinks Resolved

  I have a customer who is asking the following questions: Can you explain the difference between Table 12 and Table 13 in the data sheet? It appears that Table 13 is referring in interleaved converters? Can you explain what is meant by this? The reason...
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  Jim Brinkhurst1

  • over 3 years ago
  • Data converters
  • Data converters forum

  RE: ADC12J2700 JESD204B setting ???

  Hi Stephen For that mode and K value, the following register write sequence will configure the ADC as needed. This is for foreground calibration mode. 0x0021 0x00 // Initiate reset of all registers 0x0021 0x01 // De-assert reset 0x0030 0x00 // SYSREF...
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  Jim Brinkhurst1

  • over 3 years ago
  • Data converters
  • Data converters forum

  RE: ADC12J2700: Should the ADC12J2700 have spurs at 1/2 and 1/4 of the sampling frequency?

  Hi Layne The ADC12J2700 ADC uses a 4-way interleaved architecture. A built-in calibration process is used to minimize the offset mismatch between interleaved cores, but there will be some residual mismatch after the calibration process completes. That...
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  Jim Brinkhurst1

  • over 3 years ago
  • Data converters
  • Data converters forum

  RE: ADC12J2700 JESD204B Channel rate?

  Hi Zhu For the M=8 portion of your question, there is a detailed explanation of why that is done here: https://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/432366 For your case in the data rate calculation you can consider...

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