Part Number: ADC12J2700 Hello.
Can someone tell me what instantiates the biasing of the JESD pins? These are the DS [7:0]_P and DS [7:0]_N pins of the device. Is the biasing established automatically on powerup or is it a result of some SPI command…
Part Number: ADC12J2700 I am trying to use the ADC12J2700 IBIS model for Hyperlynx signal integrity simulations, but a lot of the pins within the model are undefined. I am interested in DS0*-DS4* and they are all NC in the IBIS model. Can I get an updated…
Part Number: ADC12J2700 Other Parts Discussed in Thread: LMK04828 , TPS74901 HI.
ADC : ADC12J2700
CLOCK : LMK04828
FPGA : KINTEX UlteraSCALE
It has the above configuration and is being used using Xilinx FPGA JESD204B IP. When checking the SYNC…
Part Number: ADC12J2700 Hi Team,
I now have two questions:
Configuration conditions:
Bypass Mode, No Decimation, DDR = 1, P54 = 0, LMF = 8,8,8.
DEVCLK+/-=2048MHz. FPGA is xc7vx485tffg1158-2 of xilinx.
Question 1: Although the manual…
Part Number: ADC12J2700 Other Parts Discussed in Thread: TSW14J57EVM , DAC38RF82EVM , DAC38J84EVM , , ADC12DJ5200RF Hi,
we want to test out a JESD204B link for feed-forwarding of classical data state inside a quantum computer.
We have a small analog…
Part Number: ADC12J2700 Hi,
I am looking for ZCU102 reference design package to interface with our ADC module from TI. Can you please provide the link. The link provided in this topic is broken
https://e2e.ti.com/support/data-converters/f/73/t/816433…
Deepak,
We do not have an example with the ADC12J2700 but we have an example that uses another ADC that might be helpful. This can be downloaded from the following link:
Regards,
Jim
Part Number: ADC12J2700 We are seeing bit 2 in the CAL_STAT register (0x5b) toggle occasionally if we poll that register repeatedly. We're operating with background calibration enabled, and generally read a value of 0x09 from the register, but 30-50%…
Part Number: ADC12J2700 We're using an ADC12J2700 with a continuously running SYSREF. To date we've just been using the default RDEL value, but we're seeing some board-to-board (and possible temperature related?) variations where we see the "Dirty capture…
Part Number: ADC12J2700 Hello,
My customer is using ADC12J2700. To confirm configuration I/O operation, they read the following register values:
Reg 0x003 (Chip type): 0x03 (expect 0x03) Reg 0x006 (Chip version): 0x03 (expect 0x13) Reg 0x00C-D …
