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  • ADC12QJ1600: Clock requirement - ADC12QJ1600

    TI Thinks Resolved
    Part Number: ADC12QJ1600 Tool/software: We are considering a custom design PCB with ADC12QJ1600 as a main component. What are the input clocking requirement for ADC12QJ1600 and which clock generating devices would be suitable and compatible with ADC12QJ1600…

  • ADC12QJ1600: ADC12QJ1600

    Part Number: ADC12QJ1600 Tool/software: Hello, While working with the ADC12QJ1600 at 1Ghz sample rate we encountered a problem: When driving a high signal that saturated the ADC (1.5Vpp) - we got Data Corruption - the 4 outputs suddenly loose…
    • Answered

  • ADC12QJ1600: JESD204C IP

    Resolved
    Part Number: ADC12QJ1600 Hi we are developing a 4 channel spectrum analyzer, for our intial system design and Hardware workflow in vivado, we require JESD204C IP from Texas Instruments. I request you to please provide the Vivado JESD204C IP for ADC12QJ1600…
    • Resolved
    • Answered

  • ADC12QJ1600EVM: ADC12QJ1600: test modes

    Resolved
    Part Number: ADC12QJ1600EVM Hello, we have ADC12QJ1600EVM with Zynq FPGA using TI JESD204 IP HDL stack. The settings are JMODE3 (10bit resolution), Fs=500Msps, F=5, K=32. The FPGA design uses just one RX lane. It seems to be somehow working, QPLL is…
    • Resolved
    • Answered

  • ADC12QJ1600: ADC12QJ1600

    Resolved
    Part Number: ADC12QJ1600 Tool/software: Hello, I have a question: We have successfully integrated the latest JESD204 IP core in Xilinx ZU19EG chip. We need to know how do we instantiate the core X8 times with different GTH/GTY and SERDES banks in…
    • Resolved
    • Answered

  • ADC12QJ1600: ADC12QJ1600

    Resolved
    Part Number: ADC12QJ1600 Tool/software: Hello, Do you have a test module of the ADC12JQ1600 for Modelsim or for Cadence simulator? Regards, Giora
    • Resolved

  • ADC12QJ1600: ADC12QJ1600 High Speed Data Converters

    TI Thinks Resolved
    Part Number: ADC12QJ1600 Tool/software: Hi Team, We are making use of an ADC12QJ1600 ADC IC. Is it possible to control the analog inputs (INA+/- & INB+/-) with high-speed serialized output (D0+/- to D3+/-) only and similarly for the analog inputs (INC…

  • ADC12QJ1600: Enabling sample lanes on TI JESD204C IP core

    Part Number: ADC12QJ1600 Hi, are the lane samples (rx_lane_samples) outputs of the TI IP core available for the JMODE8 (64B66B, 12bit resolution, 4 lanes).? Is laso not clear form the User guide what are the TL_PARAM I set the IP core parameters like…

  • ADC12QJ1600-SP: ADC Synchronization using one FPGA

    Part Number: ADC12QJ1600-SP Other Parts Discussed in Thread: ADC12QJ1600 Hi, We are attempting to synchronize the data output from two TI ADC12QJ1600 ADCs into one FPGA. We have reviewed TI’s documentation and demo of synchronizing two ADCS using two…

  • ADC12QJ1600: ADC12QJ1600 in JMODE0

    Part Number: ADC12QJ1600 Other Parts Discussed in Thread: TSW14J58EVM , TSW12QJ1600EVM , Tool/software: Hello! I'm trying to read ADC12QJ1600 with an FPGA. I'm using the TI evaluation boards TSW14J58EVM and TSW12QJ1600EVM. I have turned off additional…

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