Part Number: ADC12QJ1600-SP Other Parts Discussed in Thread: ADC12QJ1600 Hi,
We are attempting to synchronize the data output from two TI ADC12QJ1600 ADCs into one FPGA. We have reviewed TI’s documentation and demo of synchronizing two ADCS using two…
Part Number: ADC12QJ1600-SP Other Parts Discussed in Thread: ADC12QJ1600 Tool/software: I am trying to program via SPI the initialization sequence for bringing up the ADCs. It looks like I have the correct values and sequence and have verified that timing…
Part Number: ADC12QJ1600-SP Why does the datasheet specify an output impedance of 300Ohm for the PLLREFO and TRIGOUT outputs? In Section 7.5, under the CLOCK AND TRIGGER OUTPUTS section, the datasheet spec's 720mVpp differential output voltage into a…
Part Number: ADC12QJ1600-SP We are thinking of using the ADC12QJ1600-SP in one of our designs but we have some questions about selecting J-Modes for the JESD204C Interface.
Table 8-15 in the datasheet shows the available operating modes along with their…
Part Number: ADC12QJ1600-SP The ADC datasheet says that "TI Strongly Recommends that CLK± be AC-coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self-bias to the optimal input common-mode voltage for best performance." Thus suggesting LVDS as the…
Hi Rob,
Rob Reeder said: I would just check to make sure they are not above the abs max of the FPGA.
Thank you. Let me know any update.
Following e2e thread shows LVPECL interface should be used for CLK± of ADC12QJ1600. But as shown in XCKU5P datasheet…
Part Number: ADC12QJ1600EVM Other Parts Discussed in Thread: ADC12QJ1600-SP Tool/software:
My team has set up a system using your ADC12QJ1600EVM connected to a Xilinx VCK190EVM board over the FMC bus to do sampling of 4 analog inputs at a 1.6Ghz rate…
