Hi Giora,
I believe the papers that Eric suggested spells out how to do a jitter analysis on your clock distribution design.
Simply RSS (root-sum-square) each clocking device as they cascade to each other, the sum total jitter will be the jitter presented…
Part Number: ADC12QJ1600EVM Tool/software: hello,
I under stand that the LMK can accept on clkin1 in pin in distribution mode up to 3Ghz.
I wish to design a system according the below diagram (Figure B-1. ADCxxQJxx00EVM Clocking System Block Diagram…
Part Number: ADC12QJ1600EVM Other Parts Discussed in Thread: LMK04828 Tool/software: hello,
I am confused -Refiring to ADCxxQJxx00EVM data sheet - the input to CLKIN1 (see image) can be between 500-1600Mhz input.
The data sheet of the LMK04828 claim max…
Hello Terry,
The schematic for the EVM is a little confusing, by default the board is configured for single ended to differential operation, even though those components show as DNI on the schematic.
Yes the opposite polarity of the inputs is swapped…
Part Number: ADC12QJ1600EVM Other Parts Discussed in Thread: ADC12SJ800 , ADC12QJ1600 Tool/software: Hi all,
we would like to use different balun than used on ADC12QJ1600EVM.
Is it possible to use TCM2-63WX+ instead of TCM2-43X+?
Can you provide S-params…
Part Number: ADC12QJ1600EVM Tool/software: Dear all,
can you provide schematics and possibly also layout so we can check FMC connector pinout and select suitable Xilinx FPGA kit?
Thank you,
Michael
I am also interested in the answer to this question, and if I may piggyback a followup on it: The family Xilinx Artix UItrascale Plus is not listed as supported while both higher and lower performance device families are. Are chips such as the XCAU15P…
Part Number: ADC12QJ1600EVM Other Parts Discussed in Thread: ADC12QJ1600 Hi TI,
I want to modify J3 and J5 of ADC12QJ1600 EVM to differential input.
Follow the recommendations on page 28 of the ADCxxQJxx00 Evaluation Module User's Guide.
Remove C26…