Hello Rob, It seems there was a miscommunication between me and the test engineer. Let me explain what is happening. For any 8b/10b modes, like JMODE0, the capture card gives an error like the ones below.
While using a 64b/66b JMODE, this does not happen…
Part Number: ADC12QJ1600EVM Tool/software: While the end target is using an ADC12QJ1600EVM this is really about the TI204C-IP.
I apologize for this very basic question, but I am not well versed in JESD204 or Xilinx Vivado.
I am merely trying to the…
Part Number: ADC12QJ1600EVM Tool/software: Hi team,
In ADC12QJEVM, there are four types of clock source as follows. - On board50M Ref to ADC PLL - Ext Direct CLK to ADC - Ext Ref to ADC PLL - Ext CLK from LMK to ADC
Why is there no option to use like following…
Part Number: ADC12QJ1600EVM Other Parts Discussed in Thread: ADC12QJ1600 Tool/software: Hello all,
In the ADC12QJ1600 EVM GUI, the low-level internal register map can be exported to form a sort of SPI programming file for the ADC. However, this exported…
Part Number: ADC12QJ1600EVM Other Parts Discussed in Thread: ADC12QJ1600 Tool/software: Hi Team,
Customer is asking if TSW14J56 support ADC12QJ1600EVM 8B/10B JMODE? (JMODE 0/1/2/3/9/10)
Thanks.
Part Number: ADC12QJ1600EVM Tool/software: Tried Multiple GUI utilities over the course of a couple of days but same issue persists.
The GUI is unable to find the device.
- GUI software installer: sbac269 (also tried sbac266, same issue)
- OS: windows…
Part Number: ADC12QJ1600EVM Other Parts Discussed in Thread: ADC12QJ1600 Tool/software: Hi,
I am working with ADC12QJ1600EVM using the GUI software to evaluate the proper configuration for my design. Now, that I have that configuration, I want to implement…
Part Number: ADC12QJ1600EVM Other Parts Discussed in Thread: ADC12QJ1600 , Tool/software: Hi,
I am using the ADC12QJ1600EVM GUI to configure the ADC12QJ1600 device in the evaluation board. I am using the clock source as OnBoard 50M Ref to ADC PLL . Once…
Hi Giora,
I believe the papers that Eric suggested spells out how to do a jitter analysis on your clock distribution design.
Simply RSS (root-sum-square) each clocking device as they cascade to each other, the sum total jitter will be the jitter presented…
Part Number: ADC12QJ1600EVM Tool/software: FPGA Reference Clock is displayed in GUI and is equal to serial rate/64. Where is this needed, it is not an input of output of the device.
Is this specifying how the FPGA transceiver is to be configured?
Is…
