Answered

• ADC12QJ800-Q1: CRC errors and limited data stream with TI JESD204 IP 66b66b encoding JMODE8

  

  Mohan Karthikeyan Manickam

  Resolved

  Part Number: ADC12QJ800-Q1 Other Parts Discussed in Thread: ADC12QJ800 We are currently in the process of developing a new data acquisition system for one of our products using the ADC12QJ800 interfaced to the TI-JESD204 IP modified from the zcu102 reference…

  • Resolved

  • over 1 year ago
  • Data converters
  • Data converters forum
Answered

• ADC12QJ800-Q1: Sampling rate

  

  Robert Charbine

  Resolved

  Part Number: ADC12QJ800-Q1 Hi There, The ADC has 800 MSPS so it must be for each channel (A, B, C, D). I mean sampling rate will not split between channels. Please confirm.

  • Resolved

  • over 1 year ago
  • Data converters
  • Data converters forum
Answered

• ADC12QJ800-Q1: Register configuration problem

  

  Amy Luo

  Resolved

  Part Number: ADC12QJ800-Q1 Hi team, One of our customer's issues, I'm forwarding it below, could you please provide some troubleshooting suggestions? Requirements: The device input clock uses a differential clock: Input 144MHz, Use CPLL to generate…

  • Resolved

  • over 1 year ago
  • Data converters
  • Data converters forum

• ADC12QJ800-Q1: How to splice the data received by the FPGA receiving end and sent by AD?

  

  Katherine Wang

  TI Thinks Resolved

  Part Number: ADC12QJ800-Q1 Other Parts Discussed in Thread: ADC12QJ800 Hi Team, I'm u sing the ADC12QJ800 chip's JMODE0 mode to collect data. Could you tell me how to splice the data received by the FPGA receiving end to obtain the sampling data?…

  • over 1 year ago
  • Data converters
  • Data converters forum

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